how tap cell is used to prevent latchup effect

Hi Folks,

Can any one explain how tap cell is used to prevent latchup effect.
I know tap cell is used to connect n and p substrate to Vss and vdd respectively. In google I found one more definition tap cell is reduce resistance between vdd and vss.



Thanks in advance,
kpsr

he CMOS Inverter structure creates two parasitic transistors namely PNP & NPN as shown in enclosed Fig.These transistors so exist such that each collector drives the Base of the other BJT. This results in formation of a pnpn switch that exists across VDD/VSS supply line.When the breakdown voltage of parasitic
switch is less than the CMOS Inverter supply voltage, the switch turns ON resulting in failure of Inverter Function and failure due to excessive current thru parasitic switch.This process of turning ON is called LATCH UP.

The latch up problem can be avoided by increasing the parasitic switch breakdown voltage above CMOS Inverter (VDD/VSS) supply voltage.This is realized by shunting low resistance across Emitter-Base junction of parasitic BJT as shown in Fig.The resistor connected across PNP is kown as well tap and that across NPN is kown as Substrate tap.