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difference between altera and xilinx programming

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All FPGA vendors are using the industry standard JTAG interface for code download and in circuit-debugging. But they are using slightly different JTAG connector pinouts and vendor specific programming adapters.

Although some tools have certain capability to talk to chips of other vendors and might be able to download code to it, in-circuit debugging requires vendor specific programming adapters.
 
thank you sir,
and is there any difference in programming of xilinx and Altera.
 

In what way do you mean programming? if you mean configuring the chips the question has already been answered.
 

I suggest to ask a clearer question.

In usual terms, the HDL (high level description language, e.g. VHDL or Verilog) code would be considered as the logic "program". It's basically identical for all FPGA vendors, apart from the usage of specific libraries for low level features like PLLs or other dedicated hardware.
 

When I last checked, Xilinx required both pins on a differential port to be defined at the top, and they had to be connected to a differential driver/receiver in the source code. Altera allowed them to be defined as single-ended ports and then constrain them to be differential.
 

std_match said:
When I last checked, Xilinx required both pins on a differential port to be defined at the top, and they had to be connected to a differential driver/receiver in the source code. Altera allowed them to be defined as single-ended ports and then constrain them to be differential.
Click to expand...

I recall something slightly different. Altera likes it if you use the positive side in your port (without the negative side in the port) declaration and define it in the constraints as differential and it would auto create the negative side. e.g. diff_pin, pin in port declaration; diff_pin(n), auto generated.

Xilinx requires differential RX/TX IBUFGS/OBUFGS instantiated directly in the code.
 
Yes, low-level primitives are different. Altera has altiobuf_xxx primitives which can be used similar to Xilinx IBUF and OBUF, also in differential mode. But there's no specific advantage in using it.
 
ads-ee said:
I recall something slightly different. Altera likes it if you use the positive side in your port (without the negative side in the port) declaration and define it in the constraints as differential and it would auto create the negative side. e.g. diff_pin, pin in port declaration; diff_pin(n), auto generated.

Xilinx requires differential RX/TX IBUFGS/OBUFGS instantiated directly in the code.
Click to expand...

My posting was not very clear. What you say is exactly what I mean. With Altera, you don't have to do the differential stuff in the source code. You can use single-ended ports at the top, without any differential primitives.
 
Thanks sir.
As this is configuration only means we can run many task at the same
 

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