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Where we can connect the dummies in this diiferential pair matching?

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jarillak

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Hi....

i) I have a doubt regarding where we can connect these dummies whether with VDD or with the back-gate of diff.pair PMOS.If we connect with VDD,the purpose of dummy(stres,same environment to active MOS except etching variation) is not used in matching.

ii) Also if i share any one of terminal(either Source or drain) with active MOS,then other two terminals tied with back-gate,then how dummy behaves in schematic point of view?

thanks & regards
jarilak.r
 

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Hi jarillak,

The PMOS diff pair will have a separate N-Well as the body is locally connected to its source. In the matching pattern the matched diff pairs will be surrounded by the dummies. So they have to be in the same well.
So the dummy mos has all its terminals (G,S, D and B) shorted to the well potential i.e. the source of the diff pair.
The dummies are inactive so they should not effect circuit parameters. They can not be attached to the drain because the drain has a different potential than source or body of the diff pair. So again a separate well will be required.

Hope this helps : )
 

jarillak said:
Hi....

i) I have a doubt regarding where we can connect these dummies whether with VDD or with the back-gate of diff.pair PMOS.If we connect with VDD,the purpose of dummy(stres,same environment to active MOS except etching variation) is not used in matching.

ii) Also if i share any one of terminal(either Source or drain) with active MOS,then other two terminals tied with back-gate,then how dummy behaves in schematic point of view?

thanks & regards
jarilak.r
Click to expand...

i)bulk can go to source connection of matched pair with G,D,S going to VDD!.
ii)I believe we dont share diffusions in lower technology . (STI effect )
 

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