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Design Compiler is a synthesis tool not simulator. You synthesis your design in DC and generate the netlist and sdf (standard delay format) file. Then annotate this timing file in a simulator like NC-Sim and verify the timing & functionality.
depend on your compiler
after DC, you should get netlist
use APR(like Apollo) generate SDF
then add this SDF to your compiler script
(ex: in VCS add
"$sdf_annotate"a.sdo", pattern.chip, , "sdf.
log", "TOOL_CONTROL", ......"
to your testbench
reference VCS /NC user guide)
then use simulation tool trace the waveform(the same as RTL sim)
Here is the way how you do it. I am assuming your testbench code is in verilog here.
suppose your DUT top level is called rtl_top.
module rtl_top(.....);
.....
endmodule
You might have synthesized the above module using Synopsys-DC.
Now you will get a netlist corresponding to that. Try to get the "SDF" file for that netlist.
Now in your testcase do the following.
module testcase ()
rtl_top DUT (....) //Instantiating the top level netlist
initial begin
$sdf_annotate("rtl_top.sdf", DUT ,);
//here I am assuming sdf file is there in the current directory.
end
endmodule
Now you can simulate the testcase() module using modelsim.
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