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Req:Synthesisable code for FIFO

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arunragavan

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Well guys.. i need a synthesisable VHDL code for a FIFO.. asynchronous FIFO. Can anyone help me with the code and as well explain the basic workin for a asyn FIFO unit.
 

arunragavan said:
Well guys.. i need a synthesisable VHDL code for a FIFO.. asynchronous FIFO. Can anyone help me with the code and as well explain the basic workin for a asyn FIFO unit.
Click to expand...

Which FPGA family?
The easy way to use Megafunction Wizard (Altera) or Core Generator (Xilinx)
Or you need pure VHDL without arch. depencities?

See
1) IDT72V01 FIFO block diagram - this help you with FIFO operation
2) Asynchronous FIFO V3.0 November 3, 2000 Product Specification from XILINX
(good timing diagramm)
3) see attache files (Simulation and Synthesis Techniques for Asynchronous
FIFO Design Clifford E. Cummings Sunburst Design, Inc.)
(Simulation and Synthesis Techniques for Asynchronous
FIFO Design with Asynchronous Pointer Comparisons
Clifford E. Cummings, Peter Alfke, Sunburst Design, Inc., Xilinx, Inc.)

http://www.sunburst-design.com/papers/
 

pure VHDL code for FIFO without architectrural dependecies...

a synthesizable and simulatable codes for FIFO

with regards,
 

Hi,
Here is a fifo code long back I downloaded a uart code from that .....
Hope this helps!

Code: 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity dp_ram is
	generic(
		WIDTH:natural:=8;			  --data width
		ADDR_WIDTH:natural:=8	  --address width
	);
	port(
		rst      :in std_logic;								  --reset
		rd_clk   :in std_logic;								  --read clock
		wr_clk   :in std_logic;								  --write clock
		
		data_in  :in std_logic_vector(WIDTH-1 downto 0);	  --input data
		data_out :out std_logic_vector(WIDTH-1 downto 0);	  --output data
		
		rd_addr  :in std_logic_vector(ADDR_WIDTH-1 downto 0); --read address
		wr_addr  :in std_logic_vector(ADDR_WIDTH-1 downto 0); --write address
		
		rd_en    :in std_logic;								  --read enable
		wr_en    :in std_logic								  --write enable
	);
end entity dp_ram;

architecture mem of dp_ram is
	type register_array is array(natural range <>) of std_logic_vector(WIDTH-1 downto 0);
	
	signal mem:register_array(0 to (2**ADDR_WIDTH-1));
	
begin
	--citanje iz memorije
	read:process(rst,rd_clk,rd_en,rd_addr) is
			begin
				if (rst='1') then
					data_out<=(others => '0');
				else --if rising_edge(rd_clk) then
--					if (rd_en='1') then
						data_out<=mem(conv_integer(rd_addr));
--					else
--						data_out<=mem(conv_integer(rd_addr));
--						data_out<=(others=>'Z');
--					end if;
				end if;
			end process read; 
	
	write:process(rst,wr_clk) is
			begin
				if (rst='1') then
					for i in 0 to (2**ADDR_WIDTH-1) loop
						mem(i)<=(others=>'0');
					end loop;
				elsif rising_edge(wr_clk) then
					if (wr_en='1') then
						mem(conv_integer(wr_addr))<=data_in;
					end if;
				end if;
			end process write;

end architecture mem;
Code: 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity fifo is
	generic(
		WIDTH:natural:=8;
		ADDR_WIDTH:natural:=2
	);
	port(
		rst      :in std_logic;	 	 	--reset 
		clk      :in std_logic;  		--clock
		
		data_in  :in std_logic_vector(WIDTH-1 downto 0);
		data_out :out std_logic_vector(WIDTH-1 downto 0);
				
		rd_en    :in std_logic;			--read enable
		wr_en    :in std_logic;			--write enable
		
		empty    :out std_logic;		--queue is empty
		full     :out std_logic			--queue is full
	);
end entity fifo;

architecture RTL of fifo is

	signal rd_ptr:std_logic_vector(ADDR_WIDTH-1 downto 0):=(others=>'0');	--read pointer
	signal wr_ptr:std_logic_vector(ADDR_WIDTH-1 downto 0):=(others=>'0');	--write pointer
	signal cnt:std_logic_vector(ADDR_WIDTH downto 0):=(others=>'0');		--count
	
	signal valid_rd:std_logic:='0';
	signal valid_wr:std_logic:='0';
	
	signal is_empty:std_logic:='1';
	signal is_full:std_logic:='0';
	
	constant MAX:std_logic_vector(ADDR_WIDTH downto 0):=('1',others=>'0');
	constant MIN:std_logic_vector(ADDR_WIDTH downto 0):=(others=>'0');
	
	component dp_ram
		generic(
			WIDTH:natural:=8;
			ADDR_WIDTH:natural:=8
		);
		port(
			rst      :in std_logic;	
			rd_clk   :in std_logic;		
			wr_clk   :in std_logic;				
			
			data_in  :in std_logic_vector(WIDTH-1 downto 0);
			data_out :out std_logic_vector(WIDTH-1 downto 0);	
			
			rd_addr  :in std_logic_vector(ADDR_WIDTH-1 downto 0);
			wr_addr  :in std_logic_vector(ADDR_WIDTH-1 downto 0); 
			
			rd_en    :in std_logic;						
			wr_en    :in std_logic				
		);
	end component dp_ram;
	
begin

	memory:dp_ram
		generic map(
			WIDTH=>WIDTH,
			ADDR_WIDTH=>ADDR_WIDTH
		)
		port map(
			rst=>rst,   
			rd_clk=>clk, 
			wr_clk=>clk,
			
			data_in=>data_in, 
			data_out=>data_out,
			
			rd_addr=>rd_ptr(ADDR_WIDTH-1 downto 0), 
			wr_addr=>wr_ptr(ADDR_WIDTH-1 downto 0), 
			
			rd_en=>valid_rd,  	
			wr_en=>valid_wr 
		);
	
	valid_rd<='1' when (rd_en='1' and is_empty='0') else '0';
	valid_wr<='1' when (wr_en='1' and is_full='0') else '0';
	
	is_empty<='1' when cnt=MIN else '0';
	is_full<='1' when cnt=MAX else'0';
		
	main:process(rst,clk) is
			begin
				if (rst='1') then
					rd_ptr<=(others=>'0');
					wr_ptr<=(others=>'0');
					cnt<=(others=>'0');
				elsif rising_edge(clk) then
						if (valid_rd='1') then
							rd_ptr<=rd_ptr+1;
							if (valid_wr='1') then
								cnt<=cnt;
							else
								cnt<=cnt-1;
							end if;
						end if;
						if (valid_wr='1') then
							wr_ptr<=wr_ptr+1;
							if (valid_rd='1') then
								cnt<=cnt;
							else
								cnt<=cnt+1;
							end if;
						end if;
				end if;
			end process main;

	empty<=is_empty;
	full<=is_full;
		
end architecture RTL;

configuration dp_fifo of fifo is
	for RTL
		for memory:dp_ram
			use entity work.dp_ram(mem);
		end for;
	end for;
end configuration dp_fifo;

Added after 2 minutes:

Hi,
Here is a fifo code long back I downloaded a uart code from that .....
Hope this helps!

Code: 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity dp_ram is
	generic(
		WIDTH:natural:=8;			  --data width
		ADDR_WIDTH:natural:=8	  --address width
	);
	port(
		rst      :in std_logic;								  --reset
		rd_clk   :in std_logic;								  --read clock
		wr_clk   :in std_logic;								  --write clock
		
		data_in  :in std_logic_vector(WIDTH-1 downto 0);	  --input data
		data_out :out std_logic_vector(WIDTH-1 downto 0);	  --output data
		
		rd_addr  :in std_logic_vector(ADDR_WIDTH-1 downto 0); --read address
		wr_addr  :in std_logic_vector(ADDR_WIDTH-1 downto 0); --write address
		
		rd_en    :in std_logic;								  --read enable
		wr_en    :in std_logic								  --write enable
	);
end entity dp_ram;

architecture mem of dp_ram is
	type register_array is array(natural range <>) of std_logic_vector(WIDTH-1 downto 0);
	
	signal mem:register_array(0 to (2**ADDR_WIDTH-1));
	
begin
	--citanje iz memorije
	read:process(rst,rd_clk,rd_en,rd_addr) is
			begin
				if (rst='1') then
					data_out<=(others => '0');
				else --if rising_edge(rd_clk) then
--					if (rd_en='1') then
						data_out<=mem(conv_integer(rd_addr));
--					else
--						data_out<=mem(conv_integer(rd_addr));
--						data_out<=(others=>'Z');
--					end if;
				end if;
			end process read; 
	
	write:process(rst,wr_clk) is
			begin
				if (rst='1') then
					for i in 0 to (2**ADDR_WIDTH-1) loop
						mem(i)<=(others=>'0');
					end loop;
				elsif rising_edge(wr_clk) then
					if (wr_en='1') then
						mem(conv_integer(wr_addr))<=data_in;
					end if;
				end if;
			end process write;

end architecture mem;
Code: 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity fifo is
	generic(
		WIDTH:natural:=8;
		ADDR_WIDTH:natural:=2
	);
	port(
		rst      :in std_logic;	 	 	--reset 
		clk      :in std_logic;  		--clock
		
		data_in  :in std_logic_vector(WIDTH-1 downto 0);
		data_out :out std_logic_vector(WIDTH-1 downto 0);
				
		rd_en    :in std_logic;			--read enable
		wr_en    :in std_logic;			--write enable
		
		empty    :out std_logic;		--queue is empty
		full     :out std_logic			--queue is full
	);
end entity fifo;

architecture RTL of fifo is

	signal rd_ptr:std_logic_vector(ADDR_WIDTH-1 downto 0):=(others=>'0');	--read pointer
	signal wr_ptr:std_logic_vector(ADDR_WIDTH-1 downto 0):=(others=>'0');	--write pointer
	signal cnt:std_logic_vector(ADDR_WIDTH downto 0):=(others=>'0');		--count
	
	signal valid_rd:std_logic:='0';
	signal valid_wr:std_logic:='0';
	
	signal is_empty:std_logic:='1';
	signal is_full:std_logic:='0';
	
	constant MAX:std_logic_vector(ADDR_WIDTH downto 0):=('1',others=>'0');
	constant MIN:std_logic_vector(ADDR_WIDTH downto 0):=(others=>'0');
	
	component dp_ram
		generic(
			WIDTH:natural:=8;
			ADDR_WIDTH:natural:=8
		);
		port(
			rst      :in std_logic;	
			rd_clk   :in std_logic;		
			wr_clk   :in std_logic;				
			
			data_in  :in std_logic_vector(WIDTH-1 downto 0);
			data_out :out std_logic_vector(WIDTH-1 downto 0);	
			
			rd_addr  :in std_logic_vector(ADDR_WIDTH-1 downto 0);
			wr_addr  :in std_logic_vector(ADDR_WIDTH-1 downto 0); 
			
			rd_en    :in std_logic;						
			wr_en    :in std_logic				
		);
	end component dp_ram;
	
begin

	memory:dp_ram
		generic map(
			WIDTH=>WIDTH,
			ADDR_WIDTH=>ADDR_WIDTH
		)
		port map(
			rst=>rst,   
			rd_clk=>clk, 
			wr_clk=>clk,
			
			data_in=>data_in, 
			data_out=>data_out,
			
			rd_addr=>rd_ptr(ADDR_WIDTH-1 downto 0), 
			wr_addr=>wr_ptr(ADDR_WIDTH-1 downto 0), 
			
			rd_en=>valid_rd,  	
			wr_en=>valid_wr 
		);
	
	valid_rd<='1' when (rd_en='1' and is_empty='0') else '0';
	valid_wr<='1' when (wr_en='1' and is_full='0') else '0';
	
	is_empty<='1' when cnt=MIN else '0';
	is_full<='1' when cnt=MAX else'0';
		
	main:process(rst,clk) is
			begin
				if (rst='1') then
					rd_ptr<=(others=>'0');
					wr_ptr<=(others=>'0');
					cnt<=(others=>'0');
				elsif rising_edge(clk) then
						if (valid_rd='1') then
							rd_ptr<=rd_ptr+1;
							if (valid_wr='1') then
								cnt<=cnt;
							else
								cnt<=cnt-1;
							end if;
						end if;
						if (valid_wr='1') then
							wr_ptr<=wr_ptr+1;
							if (valid_rd='1') then
								cnt<=cnt;
							else
								cnt<=cnt+1;
							end if;
						end if;
				end if;
			end process main;

	empty<=is_empty;
	full<=is_full;
		
end architecture RTL;

configuration dp_fifo of fifo is
	for RTL
		for memory:dp_ram
			use entity work.dp_ram(mem);
		end for;
	end for;
end configuration dp_fifo;
 

thanks dude.. i was able to synthesis it.. what wud be the basic difference n the architecture of this FIFO when i use it n asyn communication scheme. when i need both data and signals(instructuctions - such as request and ack) to be passwed thru the FIFO for communication to commence.

with regards,
 

Hi,
Sorry The code I provided is for synchronous fifo. For
asynch fifo refer to Xilinx application notes in the link below...
**broken link removed**

Added after 28 minutes:

Hi,
From Xilinx site download xapp258.pdf and xzpp258.zip files!
 

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