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How to change w/l from one technology to another technology

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fatima1_s

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I have OTA schematic with nmos sizing is 50um/10um(w/l) and pmos sizing is 10um/10um(w/l) .this schematic is implemented in 0.35um technology. i have to implement the same schematic in 90 nm . i want to know how calculate w/l ratio for 90nm technology.
 

These sizes are more about noise and matching than strictly
current ratioing. They would probably work as-is (but be
overkill). You probably have multiple "values" that need to
be supported (power, noise, gain) and each wants something
different; the design has to cover the superset.

You could probably shrink area based on noise coefficients,
L based on gain (gm*rout, L gives rout) and W/L for your
desired operating point in the output stage (how close to
rail you can get and still have decent gain).

The noise and rout concerns may not let you move as much
as you'd think.
 

fatima1_s said:
I have OTA schematic with nmos sizing is 50um/10um(w/l) and pmos sizing is 10um/10um(w/l) .this schematic is implemented in 0.35um technology. i have to implement the same schematic in 90 nm . i want to know how calculate w/l ratio for 90nm technology.
Click to expand...

If you know the process parameters ( e.g. beta,K ) you can scale W/L ratio so that the same current flows.
But in the other hand what happens in the MOS from noise,distortion,impedance,temperature effect, etc . point of view, nobody knows...
 

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