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Verilog: How to parameterize the module's name

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redolution

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In the testbench, what I tried to do is

module_name=adder;

module_name
module_name_0(...port-mapping...);

By doing this, every time I can just change the module_name, then the dut is done automatically, i.e., if module_name=adder, then the testbench will test adder, if module_name=divider then the testbench will test divider.

I've tried parameter and 'define, all didn't work. Please help!

Thank you!
 

It's very unusual that different module instantiations have identical port maps and can be driven by the same test bench, in so far the problem will rarely occur in regular Verilog projects.

But if it's the case with your project, what's so awful with writing complete module instantiations and selecting one or the other, e.g. by `ifdef macros?
 

redolution said:
In the testbench, what I tried to do is

module_name=adder;

module_name
module_name_0(...port-mapping...);

By doing this, every time I can just change the module_name, then the dut is done automatically, i.e., if module_name=adder, then the testbench will test adder, if module_name=divider then the testbench will test divider.

I've tried parameter and 'define, all didn't work. Please help!

Thank you!
Click to expand...

What you are trying to do is not supported in the language definition, therefore it's illegal to do what you are trying to do. Maybe you should spend time reading the LRM.
 

In SystemVerilog, you can do

Code: 
`define TEST(name) test_``name

`define MODULE_NAME adder


`TEST(MODULE_NAME)

which will expand to test_adder.
 
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Nice to know that, but as I've almost never been able to use SV due to lack of support in the tools I use, I've never gone through the latest LRM that thoroughly.
 

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