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State Conductor for Asynchronous Pipeline

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MZulkarnain Jaranee

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Hi Everyone,
I'm making an asynchronous pipeline which mean every stage of pipeline control by local controller, using Quartus 2, written in VHDL language. The problem i'm facing is unversity waveform program shown that the data is not transferred between stages as shown in below images. Below image is simulated from two stages pipeline. The function of the pipeline is FIFO.



D_out is the final output from the pipeline meanwhile, D is the output from stage 1 and is the input for stage 2.

after many attempts to fix, somehow I can figure out what is the problem.
Hopefully, anyone here can help/advice me.

Fyi, there is two state only in this pipeline.
State0 - transfer data between stages when stage1 is full and stage2 is empty
State1 - disable data transfer between stages when stage 2 is full and stage 1 is empty.



The state machine is written in the state_conductor.vhd file.

Here is the code
------------- top entity ---------------------------
Code:
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity gasp is
port(
	x, y : in std_LOGIC;
	d_in : in integer;
	d_out, d: out integer
);
end gasp;

architecture gasp of gasp is
COMPONENT dfflop
		port(	
			data_in:	in integer;
			enable:		in std_logic;
			data_out:	out integer
		);
END COMPONENT;
COMPONENT gasp_ctrl
	PORT
	(
		in0, in1 : in STD_LOGIC;
		en : out STD_LOGIC
	);
END COMPONENT;	
COMPONENT state_conductor
      port(
		
		in_left : in std_logic; -- - in_left is left bit for current_state
		in_right : in std_logic; -- - in_right is right bit for current_state
		state : out std_logic -- assert low or high bit for gasp controller
		);
END COMPONENT;	
	---- state conductor wire ------
	signal state_1: std_LOGIC;
	------- enable wire ------------
	signal en_1, w, en_2, z: std_LOGIC ;
	------- data wire ------------
	signal data_wire, data_wire1 : integer ;
	begin
	
		------------ stage 1 ---------------------
		ctrl_1 : gasp_ctrl port map (in0 => x, in1 => state_1, en => en_1);
		latch_1 : dfflop port map (data_in => d_in, enable => en_1, data_out => data_wire);
		conductor_1 : state_conductor port map (in_left => en_1 ,in_right => en_2, state => state_1);
		ctrl_2 : gasp_ctrl port map (in0 => state_1, in1 => y, en => en_2);
		latch_2 : dfflop port map (data_in => data_wire, enable => en_2, data_out => d_out);
		d <= data_wire;
		
end gasp;


------------- sub module -----
------------- gasp_ctrl.vhd ----- this module responsible to enable and disable the dflipflop in dfflop.vhd --------------
Code:
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;


ENTITY gasp_ctrl IS 
	PORT
	(
		in0, in1 : in STD_LOGIC;
		en : out STD_LOGIC
		
	);
END gasp_ctrl;

ARCHITECTURE structure OF gasp_ctrl IS
	
	
BEGIN 
    en <= (NOT in0) AND in1;
END structure;

-------------- dfflop.vhd --- for store the data in stage
Code:
---------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;

---------------------------------------------

entity dfflop is
port(	
	data_in:	in integer;
	enable:		in std_logic;
	data_out:	out integer
);
end dfflop;

----------------------------------------------

architecture behv of dfflop is
begin

   process(enable)
   begin
   -- enable rising edge ----
	if (rising_edge(enable)) then
	    data_out <= data_in;
	end if;

   end process;	

end behv;
-----------------state_conductor.vhd----responsible either to transfer data between stage or no
Code:
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;

LIBRARY work;

ENTITY state_conductor IS 
	PORT
	(
		in_left : in std_logic; -- - in_left is left bit for current_state
		in_right : in std_logic; -- - in_right is right bit for current_state
		state : out std_logic -- assert low or high bit for gasp controller
		
	);
END state_conductor;

ARCHITECTURE structure OF state_conductor IS 
	type STATE_TYPE is (S0, S1);
   signal CURRENT_STATE: STATE_TYPE ;
	signal NEXT_STATE: STATE_TYPE := S1;
	signal full_empty : std_logic_vector(1 downto 0) ;
	signal en : std_logic;
BEGIN
	 
	 
	 full_empty(1) <= in_left;
	 full_empty(0) <= in_right;
	 CURRENT_STATE <= NEXT_STATE after 7ns;
	 process(CURRENT_STATE, full_empty)
	  begin	 
		 case CURRENT_STATE is
			 when S0 => state <= '0';
				if full_empty = "10" then NEXT_STATE <= S1;
				else NEXT_STATE <= S0;
			 end if;
			 when S1 => state <= '1';
				if full_empty = "01" then NEXT_STATE <= S0;
			 else NEXT_STATE <= S1;
			 end if;
		end case;
	 end process;
    
	 
END structure;
---------------------------------------------------


CIRCUIT IMAGE

 

Didn't yoiu intend to write synthesizable VHDL? In this case your design should use a clock instead of simulation timing statements like
Code:
CURRENT_STATE <= NEXT_STATE after 7ns;
I presume you're using functional simulation in the "university waveform program" (which is actually a beginners Modelsim frontend).

To narrow down why your design doesn't work as intended, you can add internal nodes to the waveform viewer. I guess, the state machine never changes state and thus doesn't generate clock edges for the DFF registers, so nothing happens.
 

Your code has a logical error in it. No matter how x and y toggle there is no possible way that the signal state_1 will ever go high as en_1 must go high for the statement full_empty = "10" to become true. Basically you have a feedback path that never changes state.

en <= (not in0) and in1;

in1 can never be 1 as it's connected to state_1 which will never go high unless you transition to state S1, which only happens on in_left = '1' (a.k.a en from above).

You need to work hard on your debugging skills (i.e. follow signals around and see if they make sense).

Also what is up with using the deprecated non-standard packages std_logic_unsigned & std_logic_arith in all your files, when you don't even do any arithmetic! I could understand (and forgive) having numeric_std included if you think you will be adding an arithmetic operation, but to not have any arithmetic operations and include a non-standard package?

- - - Updated - - -

As I was curious, I swapped the full_empty comparison so it does in_left = '0' and in_right = '1' to transition to state S1, gave the following simulation result:
Capture.PNG
 
Last edited:

- - - Updated - - -

As I was curious, I swapped the full_empty comparison so it does in_left = '0' and in_right = '1' to transition to state S1, gave the following simulation result:
View attachment 112102

Hi, Does you mean change this code
Code:
if full_empty = "10" then NEXT_STATE <= S1;
into this
Code:
if full_empty = "01" then NEXT_STATE <= S1;
??
I changed it but same error happen.. Furthermore, does it compulsory for me to do the simulation in ModelSim?
 

Furthermore, does it compulsory for me to do the simulation in ModelSim?
As said, the "university program" waveform viewer is a Modelsim frontend and basically performs the same simulations. But Modelsim has additional features like breaking a simulation and forcing signals. In so far it's a good idea to learn how to write HDL testbenches and use the generic Modelsim interface.
 

Dear Ads-EE,
Need your reply as soon as possible as I'm near to deadline.. Now I'm stuck.. Still error happen even I swapped the full_empty value...
 

Dear Ads-EE,
Need your reply as soon as possible as I'm near to deadline.. Now I'm stuck.. Still error happen even I swapped the full_empty value...

I don't know the answer, I'm not the one designing this circuit. I don't even know what your testbench does. I just looked at the feedback path through the circuit and modified the two lines:

Code VHDL - [expand]
1
2
3
4
5
6
7
-- changed the following two lines from this:
if full_empty = "10" then NEXT_STATE <= S1;
if full_empty = "01" then NEXT_STATE <= S0;
 
-- to this:
if full_empty = "01" then NEXT_STATE <= S1;
if full_empty = "10" then NEXT_STATE <= S0;



I then played with the x and y inputs and decided to give them a 180 degree phase shift. That's all I did. I'm not going to try and figure out your circuit.

FYI, IMO if you can't debug this design, trace the signal states through the design, or determine what makes the state machine transition and why it doesn't ...
The ability to do any of the those things is required by an engineer.
 
Last edited:

The ability to do any of the those things is required by an engineer.

hehe... :-D I'm not an engineer.. I'm more to programmer at high level language. Debugging code at higher languages like java, and python much easier.. I thought VHDL is like any other programming languages that I learned before, that why I took the subject this semester... After this project, I don't want to touch anything to do with VHDL. Btw, an engineer at my school did help me and he able to run it.. Thanks a lot Ads See.
 

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