mostafa272
Junior Member level 3
Hi
I created an array multiplier in schematic mode with S-edit,then I extracted spice netlist,but I don't know what is this technology process,because transistors is defined like following line:
M2 Out A Gnd Gnd NMOS W='28*l' L='2*l' AS='148*l*l' AD='144*l*l' PS='68*l' PD='68*l' M=1
I want to simulate this netlist with 0.18 micron technology,but I don't know how can I do this,please help me.
I created an array multiplier in schematic mode with S-edit,then I extracted spice netlist,but I don't know what is this technology process,because transistors is defined like following line:
M2 Out A Gnd Gnd NMOS W='28*l' L='2*l' AS='148*l*l' AD='144*l*l' PS='68*l' PD='68*l' M=1
I want to simulate this netlist with 0.18 micron technology,but I don't know how can I do this,please help me.
