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[SOLVED] (simple question)Wrapper to set all inputs and output to zero (verilog RTL coding)

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aelbad

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Hi all,

can I implement a wrapper which basically only assign all the inputs and outputs to 0 around my already synthesized block using verilog RTL code and synthesis that code into a wrapper around my already synthesized block?:thinker:

Thank you,
Cheers,
 

Of course you can. But what you will observe after synthesis of the wrapper will be that all the logic for your existing block will be optimized away.
That is because you are driving all the inputs of the existing block to 0.
One workaround could be to apply a don't touch to your existing block while synthesizing the wrapper.
 
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