P.L.L as F.M Detector

Hello, I need help in understanding the operation of PLL as FM Detector.

This is the graph of the output voltage as a function of the frequency of the input signal:

Suppose that:
- the amplitude of the input signal is 4v.
- f0 is 100kHz.

As we can see when the frequency of the input signal is equal to f0 we will get in the output of the LPF 0V.

My question is, if we will change the frequency of the input signal to the lock frequency (you can see where is it in the graph) , the voltage in the output of the LPF will be 4V? (I know that after fLock1 and fLock2 the voltage will be zero of course as we can see in the graph).

Not necessarily 4V. The output from the LPF will (within locking range) be proportional to the frequency difference but what it actually is will depend on the design of the phase detector and the sensitivity of the VCO to voltage changes.

Brian.

The lock detector is shifted in phase to produce max voltage when synchronous , whereas the loop detector is at mid-scale voltage giving negative feedback on phase error at all times within the constraints.

Since the lock detector peaks when locked, the feedback would be either positive or negative making the loop unstable.

There are many types of detectors. balanced bridge, XOR Type I ( both frequency doublers which mix the entire cycle) the transfer function is recursive and has a finite capture range and Type II phase/frequency detectors which are edge sensitive but infinite capture range and then synchronous multiplier, integrate and dump detectors, which give better noise immunity and perform a convolution integral of phase error with a matched filter on receiver input.