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How to generate sine waves using verilog?

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keerthna

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How to generate sine waves by using a verilog code? Can anyone please explain in detail? I heard about the look up table but have no clue on how to implement on FPGA? Can anyone post a sample code to help ?
Thanks in advance
 

How do i know if my FPGA supports such an ip core or not?
 

By reading the documentation of the fpga vendor? Anyways, Xilinx & Altera both offer DDS cores. So if you use Xilinx you already had your answer in post #2. If you use Altera you now have your answer in post #4. And if you use another fpga vendor then post #5 is an excellent place to mention which fpga you are using. ;-)
 

I use spartan-6 FPGA from xilinx
 

I assume the Xilinx DDS generator isn't available in the free ISE/Vivado WebPack version?
 

Well, I just checked my webpack Vivado install and I could use the DDS Compiler without problems. And I recall a similar situation with ISE for webpack.
 

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