Error in VHDL assignments

library ieee;
use     ieee.std_logic_1164.all;
use 	ieee.std_logic_arith.all;
use		ieee.math_real.all;

library work;
use		work.fft_pack.all;

entity fft_g is
	generic(
		Dwidth		: integer:=8;
		Twidth		: integer:=8;
		N			: integer:=8;
		log2N		: integer:=3;
		pipelined	: integer:=2;
		ifft		: boolean:=false);
	port(
		clk			: in  std_logic;
		rst			: in  std_logic;
		en			: in  std_logic;
		p_I			: in  fft_data(N-1 downto 0);
		p_Q			: in  fft_data(N-1 downto 0);
		x_I			: out fft_data(N-1 downto 0);
		x_Q			: out fft_data(N-1 downto 0);
		overflow	: out std_logic_vector(log2N-1 downto 0));
end fft_g;

architecture rtl of fft_g is
	signal in_ifft_I		: fft_data(N-1 downto 0);
	signal in_ifft_Q		: fft_data(N-1 downto 0);
	signal out_ifft_I		: fft_data(N-1 downto 0);
	signal out_ifft_Q		: fft_data(N-1 downto 0);
    
    signal sigtmp_I			: sig_tmp(log2N downto 0, N-1 downto 0);
    signal sigtmp_Q			: sig_tmp(log2N downto 0, N-1 downto 0);

begin

fft_x : if ifft=false generate
	pas_de_croisement : for k in 0 to N-1 generate
		in_ifft_I(k) <= p_I(k);
		in_ifft_Q(k) <= p_Q(k);
		x_I(k) <= out_ifft_I(k);
		x_Q(k) <= out_ifft_Q(k);
	end generate pas_de_croisement;
end generate fft_x;
	
init : for j in 0 to N-1 generate		
	sigtmp_I(0,j) <= in_ifft_I(j);
	sigtmp_Q(0,j) <= in_ifft_Q(j);
end generate init;
		
end rtl;

type fft_data is array(natural range <>) of std_logic_vector(7 downto 0);
type sig_tmp is array(natural range <>,natural range <>) of std_logic_vector(7 downto 0);