architecture for 4 bit ripple couner using structural model.

Code VHDL - [expand]
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structural code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ripple_counter_4bit is
    Port ( count : in  STD_LOGIC;
           reset : in  STD_LOGIC;
           a : out  STD_LOGIC_vector(o to 3));
end ripple_counter_4bit;
 
architecture Behavioral of ripple_counter_4bit is
component dff port(d_in,clock,reset:in std_logic;
                         d_out:out std_logic);
                         end component;
 begin
d1:dff port map(~a(0),count,reset,a(0));
d2:dff port map(~a(1),a(0),reset,a(1));
d3:dff port map(~a(2),a(1),reset,a(2));
d4:dff port map(~a(3),a(2),reset,a(3));//this is line 44.
end Behavioral;
/////////////////////////////////////////////////////////////////////////////////////