dipin
Full Member level 4
hi,
in verilog coding is there any relation between clock latency and pipelining????
in a xilinx ip core if i choose maximum pipelining for 16 bit input latency is 9 and for optimal pipelining latency is 6 and with no
piplining latency is 2.
i have used xilinx square root ip.
please give me some information.
thanks & regards
in verilog coding is there any relation between clock latency and pipelining????
in a xilinx ip core if i choose maximum pipelining for 16 bit input latency is 9 and for optimal pipelining latency is 6 and with no
piplining latency is 2.
i have used xilinx square root ip.
please give me some information.
thanks & regards