Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Methods to control Flux-walking in HF transformers

Status
Not open for further replies.

mrinalmani

Advanced Member level 1
Joined
Oct 7, 2011
Messages
463
Helped
60
Reputation
121
Reaction score
58
Trophy points
1,318
Location
Delhi, India
Activity points
5,285
How to implement control circuitry for preventing flux-walking in a full bridge topology?
The total series resistance of MOSFET and transformer primary is around 4mohm, so no question of self adjustment due to IR drop.

If higher peak-current is made alternate (ie. if peak-current has grater magnitude in Nth pulse then in (N+1)th pulse magnitude will be made higher than (N+2) pulse and so on...), would it work?
Thanks
 

In a current mode converter with a CT looking at the Tx primary current - flux staircasing is not a problem.

If not current mode you can put a suitably sized cap in series with the primary.

Your method is not well described enough to say whether it would work - its looks doubtful.
 
Thanks for the reply.
Please could you explain with a bit more detail, the logic behind current mode control.
 

Unitrode (now Texas Instruments) long ago created a current control IC to supplement the ubiquitous 3524 and which worked very similarly. It includes automatic symmetry correction for push pull converters to avoid flux staircasing.

Go the the TI website and download the UC3846 datasheet.
 

Thanks for the reply.
But this IC is slightly expensive for my purpose. Approx 2$ @ 1K units.
A rough budget for my inverter is around 25$ @ 100 units.
Are there other ways to go about it? Also, whats the basic logic behind current mode control. Just a brief description.
Thanks
 

I would study the block diagram in the datasheet, and perhaps attempt to recreate with discrete ICs.
 

If you leave sufficient dead time in the mosfet drive, e.g. 5% then there is a natural reset of the core flux as long as the applied volt seconds are not too different, and this generally keeps the core flux with in reasonable bounds, the exceptions are pulse loads which are odd multiples of the switching half period long.
 
Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top