[SOLVED] Having trouble with VHDL syntax, can anyone help me please. New to forum and VHDL.

Code VHDL - [expand]
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library ieee;
 
use ieee.std_logic_1164.all;
 
--additional functionality of being able to shift both up and down
--DIRUP=’1’ then DIN will shift into the least significant bit Y(0)
-- If DIRUP=’0’ then DIN will shift into the most significant bit Y(7)
 
 
 
entity shiftd is
    port (
        din : in std_logic; -- DATA IN
        en : in std_logic; -- CHIP ENABLE
        clk : in std_logic; -- CLOCK
        y : out std_logic_vector(7 downto 0); -- SHIFTER OUTPUT
        dirup : in std_logic); -- SHIFT DIRECTION
end shiftd;
 
architecture shiftd_arch of shiftd is
 
--SIGNALS
signal s_register : std_logic_vector (7 downto 0); --REGISTER CONTENTS
begin
 
--PROCESS : SHIFT
shift : process (clk)
begin
    if rising_edge(clk) and en='1' then -- FULLY SYNCHRONOUS AND ENABLED
      
      if (dirup = '0') then
        for i in 7 downto 1 loop
          s_register(i) <= s_register(i-1); -- SHIFT ALL BITS UP 1
        end loop;
        s_register(0) <= din;  -- INSERT DATA BIT IN LSB
              
      else if (dirup = '1') then 
        for j in 1 to 7 loop 
          s_register(j-1) <= s_register(j); -- SHIFT ALL BITS DOWN 1
        end loop;
        s_register(7) <= din;  -- INSERT DATA BIT IN LSB        
      else null;
            
      end if;         
          
    else null; --else null for original if statement
    end if; --for original if statement
end process;
 
y <= s_register; -- WRITE REGISTER CONTENTS TO OUTPUT
 
end shiftd_arch;