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Voltage based latch sense amplifier with tail NMOS transistor

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surya92

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Can someone help me understanding the effect of mismatch in the offset voltage of sense amplifier and how it behaves by playing with sizes of the transistors?
Also how to reduce the offset by reducing mismatch in the circuit?
 

Offset voltage reduces inversely proportional with the size of the (symmetrical and adjacently placed) differential input transistors, s. Pelgrom's well known paper "Transistor matching in analog CMOS applications", which you can find here in this post.
 

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