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Help needed to understand the pre and post layout simulation results.

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ghegde

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Hello,
I have designed a Clock buffer(Inverter chain buffer).
Here are my pre(schematic ) and post layout simulation data,


Parameter Pre Post
Static current14.79pA57.31pA
Peak current7.99mA7.03mA
Avg. current 0.671mA0.628mA

Definition:
Static current : Current drawn when input signal is Zero.
Peak current : Peak current drawn when the circuit is active (i.e when signal is applied to input).
Avg. current : Average current drawn when the circuit is active.

Now my question is,
1) Whether these results are expected?
2)There is a huge increase in static current(while other two are reduced). What could be the reason?

I am using AMS 0.35um technology.It is a 6 stage inverter chain.


Thanks :)
 

Try measuring the Static current at a higher temperature. The leakages would be higher and you might be able to spot where it is coming from.

It is probably due to some well diodes which were not modelled in the pre-layout. The leakages of the diodes added up.

The others numbers(Peak and Avg) look OK.
 
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    ghegde

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Thanks Nitishn5 for the reply.
I am newbie in this field,so can you please help me to know, what are the different technique usually followed to identify the leakage in layout?Any reference to book or weblink will be useful.

Thanks :)
 

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