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Ring Oscillator Phase Noise Questions

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danda821

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Hi,

I am designing a differential ring oscillator using 0.13 technology. I used four Maneatis symmetric load delay cells. I can get it oscillate ( around 2-4GHz). But the phase noise is always very large (around -60dBc/Hz at 1MHz offset).

Thank you.
 

What is the current in your delay cells?
Have you checked the tail bias current source quality?
Do you load oscillator by a heavy external load?
The basic design you describe is quite robust and should easily bring you in range of -80dBc/Hz, unless something drastic is missed.
 

The tail current is around 0.8mA (for each delay cell). Load size is 10um/0.12um, current source size is 50u/0.2u, source-coupled nmos is 12u/0.12um.

I have tried to use an ideal current source, same result.

And there is no heavy external load.

thank you.
 

0.8mA per stage looks on the low end to me. I'd go for 3-5mA or more, if noise is important.
But this alone can not explain that high noise.
I'd re-check your simulation setup. Is a good convergence achieved?
 

I have got it oscillating at 1.4GHz with PN@1MHz=-91dBc/Hz. I am wondering if it posssible to push the PN to around -100dBc/Hz. The tail current is around 1mA.
 

This time the numbers look about right. Is 1.4GHz your target or you need 2-4GHz like you mentioned initially?
I doubt you can get to -100dBc at that small current, especially if you targeting 4GHz.
You need to spend much more current for this.
 

Hello everyone!
Can someone tell me how to simulation the phase noise and jitter about PLL?
 

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