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online adder and signed digit vhdl code conversion problem

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ghattas.akkad

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Hello guys!
i have implemented the following online adder for signed digit using vhdl code
and i have simulated my design according to the example table shown in the figure attached
the problem is i am not getting the first result which is "10" for Z+ and Z+ and at some point a combination of XX and YY gives different ZZ

add1.png

add2.png

i also did not understand the happening operation since if i normally add the given bits
i do not obtain the same result
is there a special conversion happening?
 

87 views and no replies. Maybe you should have posted your VHDL code, showing how you implemented the adder, and the testbench that shows you've tried to test it. And perhaps a description of when (time in the simulation) you get the first result that is in error.

Regards
 

Sorry I added design.I have tried an example of 11111111 - 11111111 to check whether the result is satisfying but I did not get a 0000 0000 result in the simulation, although I got the table result by simulating the same input values in the figure this is what I am not getting to understand
 

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    simexp.png
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  • add_sig.zip
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Did you include the testbench code in that zip? That helps if you want people to run the simulation in an effort to help you solve the problem.
 

i did not create a test bench file i did a manual simulation by forcing the variables to the chosen value on each cycle
 

Hello Again, i have solved the pending issue of the output it turned out that initially i am not setting the inputs to 0 each and they are assigned the unsigned value. after assigning 0 to each input and inputting 0's for 3 consecutive clock cycles before starting the bit stream I have obtained the correct subtraction result
 

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