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Why don't we go for fingering of the gate length of the device?

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Yathin P U

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Hi,

I know we do the fingering of the width in order to reduce the output parasitic cap and share the diffusion. I would want to know why length of the device is not fingered.
For an instance, if I am using 90nm pdk and one of the devices has gate length of 180nm, is it advisable to finger the length of the device to 90nm and 90nm?
:thinker:

Thank you!
 

Yes we do, but it's not a fingering but segmenting long tranistors with halo implants. Below You have an example:
segmented_fet.png

The reason for this is dependency of threshold voltage mismatch coefficient to transistor length and bias conditions in these technologies
 
That's what you'd call self-cascoding, and it works well (better
than a single long gate) in some cases, but can also have some
issues relating to what the mid-node gets up to away from DC
(charge pumping, RTN, etc.). But the usual reasons for fingering
(interconnect current capacity, gate resistance) don't really
apply to L.
 
I'm talking about mismatch minimalization of long channel mosfets with halo implants. The mismatch Avth coefficient could increase few times for long channel transistors so to avoid it the long channels fets are segmented as series connection of few short channel devices.

Check this papers:
https://www.sciencedirect.com/science/article/pii/S0038110110002364
**broken link removed**
 
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