How to do 5v tolerance in 0.18um procee ?

0.18um +5.5v

Dear All:

Does any one do that , 5v tolerance in the 0.18um process ?
We device just have 3.3/1.8v . I need 5v tolerance I/O and som circuit will use 5v
. Does anyone have good idea ?

charge pump design 5v tolerance

Hi,

Your five volt concept seems to be impossible because once you have chosen your model library file the Gate oxide thickness and other parameters define how much maximum electric field tht materials can sustain and above tht the bonds in the material will break and some kind of avalanche or tunneling phenomenon can take place. So your 5 v concept seems difucult over .18um technology. Actually the circuits are wholly designed newly for each and every technology and you can not use the same circuit topologies often.

what is 5v tolerant pad

I guess for the 3.3V devices, 5 V on the gate might be OK. Overdriving the gate is not uncommon in switched-cap circuits to reduce the ON impedance of the transistors, etc.

voltage 0.18u io

This task is only actual for tristate output buffer working on common bus.
there at least 2 dangerous issues:
1. Nwell of the PMOS connected to 3.3/1.8v VDD, drain connected to 5V external voltage. So you have forward biased diode with excessive current consumption,
and what is the worse it is condition for latch up and total destruction of the chip.
So you must design some sensor that senses the maximum of the 2 voltages - VDD or VOUT and a switch that connects nwell to this max voltage.
2 Voltage drop across drain/sorce - substrate, drain-source, gate-substrate, gate-drain/source exceeds max allowable by technology voltage, both for PMOS and NMOS driver output devices. The common solution is to use voltage divider - serial connection of transistors to reduce the votage drop across the junctions. They also need special biasing at the gate to reduce gate-silicon voltage. For this a chain of diode connected transistors is used.

ieee 5v power 3.3v tolerant transistor

It is possible. Depends for example on how many VDD pins you have. If you can have dual power supply then it would help. Then core will be 1.8V and output 5.5V.

If not you would need the step down converter (5V->1.8V) for core.

For outputs I assume you are not looking for overvoltage protection but need 5V swing instead. Then you can make it bu stacking several devices and making sure that VGS is never higher than 1.8V (or 3.3V in case of hiV devices). Tripple well would be very useful.
Such an output can not provide you the speed though and also you should be careful about the ESD. and driving capability.

psu 5v tolerance

Simply put, you should check in your models whether there is a 5 V transistor. Usually, the core voltage in a 0.18u process will be 1.8 V and 3.3 V are used for I/O. Sometimes there is an option of very high voltage transistors especially for Power circuits. So, just check whether there is a 5 V transistor. Do not Overdrive the gate when it is calibrated for 3.3 V.

five volt 0.18um device

Dear All :

Thanks your comment , our chip have use 3.3/1.8v, We want to inculde
switching regulaotr . like 5->1.8 or 5-> 3.3 so that some circuit (switching circuit)
and some I/O (ESD pad) need work on 5v , in the long time, the reliability maybe
a issue . How do we solve this problem ? Thanks

0.18 5v device

Dear mitgrace....what in exact terms do you mean by the relaibility problem. Can you elaborate more on this?

site:www.edaboard.com 3.3v 5v

To avoid reliability problems (where 5V may appear across a 3.3V gate for which it was not designed) the most common technique is to use floating N-Wells for PMOS devices in the IO.

For Output if the pad voltage goes above Vdd, then the floating N-Wells with self bias to whatever voltage is on the PAD (5Volts). If the voltage drops below Vdd than the wells self bias to Vdd.

For input case it is very simple, just drop across resistors and 1 nmos.

(Note schematics are very simplified)

5 volt tolerant with 1.8v supply

many RD want to include PWM / charge pump to analog chip, have anyone ever design this type chip ?
I think , 0.18um inside charge_pump maybe not a problem , but how about switch noise ??
if we include charge pump CKT in 0.18um , I think if we want to convert 3.3v -> 5v with 1u Cap
at least need > 500KHz ~ 1MHz switch clock , and switch large pMos for charge_pump ckt
maybe have large noise couple .. how to reduce noise couple ? in analog use large space guard-ring
sourrend "charge pump" circuit ??

5v tolerant 0.18um cmos

It's doable. I remember there are some papers in JSSC(IEEE, journal of solid state circuit). One paper is in a Nov. issue, but I can't remember the year. I guess the idea is to cascade the transistors without tuning the substrate voltage. It's very tricky.