ADC integrated in an ASIC

Hi guys,
I was wondering if you know wich types of Analog to digital converter can be integrated into an ASIC? Do u know any document I can refer to? Or any example?

Thanks so much.

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Everyone. About 100 designs per year is published in each journal -- pipeline, SAR, flash, etc.

Some of this depends on the "ASIC" target foundry flow. A
mostly-digital sigma-delta converter is popular (esp. in audio
ranges and lower) because almost any cheapo digital flow
can support it. Whereas others are needful of high quality
matching and linearity in resistors or capacitors, which may
not be available or well enough controlled / modeled to hit
the goal.

Many things "can" be done, but fewer will be satisfactory in
cost, effort or outcome. Bounding the problem improves the
solution.

Ok so basically I need to have a look to the literature for ADC solution.
Do you know of any way to compare an Asic chip with and wihout an integrated ADC? Is there any tool I can use?

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If you are just looking to -have- an ADC, rather than design
one (or even if you think designing one is the most economical
path forward) you ought to begin with your target foundry
and its list of IP provider partners. If you're going with any
major player, at any node below 250nm, you ought to find
a buttload of hard-IP ADCs offered (well, maybe some are
still in development, for 40nm and under). And I contend
that unless you've done a number of ADC designs and layouts
before, the extent of art involved says "buy" rather than
"invent" unless it's all about the process of invention and
not a timely product rollout.

Maybe i didn't explain very well my question. I'm interested ro know if there is any tool which permit to calculate the piece price of an ASIC having some features with and without an integrated ADC. Are you aware about it?

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Can't help you there. As one of my VP-GMs was fond of saying,
"cost and price are unrelated". At least, a business that is in
control of its pricing will price by value-to-the-customer, not
cost-to-fabricate.

If you're not in control of your pricing then life is not good.
It's how much of the industry operates, but it's a dismal
existence for everyone but the highly incentivized guys
at the top. The rest are just cost-components to be beaten
down along with the die size.

Philosophy aside, you could attack this by bottom-up cost
for dice of two different areas and two different complexities
of test program / test time and two different yield numbers,
assigning some yield detraction to the fancier, fussier analog
content and parameters (and perhaps the cost ratio of two
flows, one base digital and one including "mixed signal features"
where two such can be found together. You might be able to
find examples of function IP blocks that declare involved-area
and yieldability (or maybe not, until you convince them you're
a customer instead of an analyst).

Canned tools, though, I got nuthin'.