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Why does Mosfet transistors burn in my inverter ?

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abdoalghareeb

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This is my final design of 500 watt 12 to 220 inverter.

1.png

It has worked perfectly for about five weeks . and suddenly without any reason all mosfet transistors has been destroyed.
This problem happened in many inverters.
I don't know what happened.

05092014657.jpg
 

First of all, nothing happens "without any reason", you just don't KNOW what the reason is. (Which is why you posted to begin with!)

Is this a unit in production? Are you saying that many units of the same design have failed? If so, then there's apparently some underlying flaw in the design. One way to destroy all mosfets, assuming they are in a bridge configuration, is "punch through" (when top and bottom MOSFETS are both on.) I assume you are aware of this if you are designing inverters.

Your pictures show some pretty catastrophic failures-there must have been some interesting noises and smells when this occurred. How many amps is your output rated for?

Without a schematic it's impossible to guess what is causing your failures. Overvoltage? Bad bridge control circuit? Lightning? ISIS?
 

As said above, lacks few more details, anyway some points can be highlighted, such as :
1 ) The BC3xx transistors acting as gate driver, seems a bit undersized to the application
2 ) Cannot see any snubber protecting the MOSFET bank against high dv/dt spikes.
 

Ooops, didn't notice the schematic. Sorry.

To reiterate what Andre says, a snubber would be helpful.

Have you actually looked at this circuit with a scope to verify there are no excessive voltage spikes?
 

Hi,

FETs fail because of too much current (both FETs are on)
or too much voltage (voltage spikes. With your desgin it is normal the at the FET´s drain is twice your battery voltage. Don´t try to kill them.
But you should protect your FET to kill every spike that is more than the rated FET voltage.

Another possibility is that if your duty cycle of one FET is different form the other, then (depends on transformer) you may see core saturation, causing high current.

With that high currents you need to carefully layout your PCB to avoid stray inductance.

Klaus
 

KlausST said:
FETs fail because of too much current (both FETs are on)
Click to expand...

At the firmware side, in fact this certainly would be the most probable cause of the failure, assuming it have not on code a limit for somewhat bellow 50% for each side, This period when both transistors are mutually not conducting is called 'dead time'.
 

For safety, it is quite usual employment fuse in series with the battery. That certainly would not prevent the burning of the Mosfet, but would prevent the rest of the board to enter fire.

You battery is rated to 12v/100Ah !
 

What is the snubber protecting?
Could you post an example .
 

Another thing to consider: even though punch-through is not a problem with this topology, if the the mosfet is turned on for any length of time the only thing to limit the current would be the DC resistance of the transformer (which is probably not much). In other words, if your PWM stops in the high state because of a software malfunction, ==> POOF!!!
 

In my code , the duty cycle sets depending on feedback signal,
and if duty cycle value increase over 48% (maximum duty cycle) the inverter will stop.
This is the output waveform on mosfet's Drain pin:

12072014580.jpg
 

Hi,

waveform looks like expected.

note the high peak. I see about 35V, but maybe it is higher. If it is more than 55V then it may harm your MOSFET.
Use a TVS with voltage more than twice of max. battery voltage.

Why stop inverter if over 48%? Why not just limit it to 48%?

Try to be sure that both halfwaves are symmetrical.
*Maybe by updating (for both sides) it just after falling edge of negative halfwave (and not after falling edge of positive halfwave).
This prevents DC because then you are sure that both halfwaves see the same duty cycle.

It is more safe to toggle channels with hardware. maybe a toggle flipflop triggered with falling PWM edge, that switches between both channels. Then you need just one PWM

Klaus
 

If the rise time of the spike is limited by the scope bandwidth, chances are it may be higher than what you see. So the clamp inbuilt-Zener may not be able to handle an external load dump of stored energy. e.g. motor load with inertia.

In this case additional clamps and snubbers based on power capacity of inverter and possible load dumps in Joules.
I deleted my previous comments after viewing your waveforms.
 

In some case the output waveform on mosfet's Drain pin is look like this:

20092014016.jpg

And the waveform on mosfet's Gate pin is look like this:

20092014017.jpg

I tried RC snubber protecting but nothing happened.
How can I remove these spikes .
 

abdoalghareeb said:
In some case the output waveform on mosfet's Drain pin is look like this:

View attachment 109551

And the waveform on mosfet's Gate pin is look like this:

View attachment 109552

I tried RC snubber protecting but nothing happened.
How can I remove these spikes .
Click to expand...

Why don't you show both traces at once? It's pretty hard to correlate anything the way you've shown it. But assuming you've got the same time scale, things don't look right. You should see the low time of the drain voltage equal the high time of the gate voltage; that's obviously not the case. Basically, you should see the drain voltage swing between battery voltage and ground, and you've got some intermediate voltage there which looks very wrong. Hopefully you have a four channel scope and can show gate and drain voltage for both phases simultaneously-that would go a long way towards resolving this. At the very least, show gate and drain voltage simultaneously.
 

Hi,

you should see the drain voltage swing between battery voltage and ground, and you've got some intermediate voltage there which looks very wrong.
Click to expand...

this is a center tapped transformer.

Then you see low, when the FET is turned ON (low ohmic)
you see battery voltage when both FETs are OFF
and you see about twice battery voltage when opposite FET is ON.

For me the waveform looks allright.

Klaus
 

why your circuit have no fault protection built to design in to avoid costly mistakes? after the design is proven, then take the fault protection out if volume/cost are super important.
 

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