Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

what does this F means in Digital output

Status
Not open for further replies.

root2hell

Member level 3
Joined
Aug 13, 2014
Messages
63
Helped
2
Reputation
4
Reaction score
2
Trophy points
8
Location
India
Activity points
394
i am performing an OR operation on two waveforms shown in attached image.
but i am getting "F" on falling edge.
why is this happening.
and how to overcome this problem. F.JPG
 

I think, you should have reviewed the PSpice reference, chapter about digital devices first.

"F" means falling edge. If it's a problem depends on your usage of the circuit.
 
what to do if i want exact 1 in place of that F.
 

Send the slow edge through a comparator or ST-gate before the OR gate.
 

from slow edge Do you mean to say low frequency signal?
 

Slow edge (slow rise- and fall-time) would be my description of the red waveform in your original post.
 

i cant change the slow rise and fall as it against my need.
 

You don't need to remove the low-pass, but you shouldn't send the low-pass filtered signal to a digital gate. Or if you do, you must be aware of unpredictable output signals.
 

OR'ing these two analog signals into a HC logic device simply delays the falling (F) edge only.

However if any ripple exists it will be amplified and may cause multiple transitions on the falling edge.

What is the intent?
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top