shizu
Newbie level 1
Hello I'm working with fpgas and I have some basic questions:
what is a netlist? from what I've read online it's a textual representation of a schematic :thinker:
what is a back annotated netlist?
why is wait not synthesizable?
thank you!
what is a netlist? from what I've read online it's a textual representation of a schematic :thinker:
what is a back annotated netlist?
why is wait not synthesizable?
thank you!