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How to reduce usage of bonded IOBs

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arishsu

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When I simulated my verilog code, the following warning is shown.

Code: 
WARNING:Xst:1336 -  (*) More than 100% of Device resources are used
Device utilization summery is as below.
Untitled.png

These are my input/output parameters.
Code: 
input clk,reset;
input[2:0]prec_sel;
input[5:0]prec_bit;
input[63:0]a,b;
output [63:0]p_d;
output [31:0]p_s;
output reg[24:0]p_16;
output reg[16:0]p_8;
output reg mode_sel_error;
output out_rdy;

How can we reduce the number of bonded IOBs?
 

In no particular order...

a. Change buses into serial inputs.

b. Using a bigger part

c. Making intelligent design decisions based on your requirements (and your parts), this is typically what you do in the upfront design

d. Time multiplex the input and output buses

e. Reading the datasheet first and realizing you have only 172 IO available but need 230, then go back to a-d.
 
ads-ee said:
In no particular order...

a. Change buses into serial inputs.

b. Using a bigger part

c. Making intelligent design decisions based on your requirements (and your parts), this is typically what you do in the upfront design

d. Time multiplex the input and output buses
Click to expand...

What is actually mean by using a bigger part?
 

IOBs are the pins on the device. If you need more pins, you need a device with more pins ie. a larger part.
 
The number of available IO is present in the FPGA name. So the current FPGA will have 172 in it's name.So select an FPGA having a bigger(or sufficient) number to accommodate all the existing IOs.
 

sharath666 said:
The number of available IO is present in the FPGA name. So the current FPGA will have 172 in it's name.So select an FPGA having a bigger(or sufficient) number to accommodate all the existing IOs.
Click to expand...
What like this Xilinx FPGA part name: XC7K325T-2FFG900?

Well sorry to disappoint you but that part doesn't have 900 user IO. It has 16 GTX, 350 HR, and 150 HP IOs. So in the case of general purpose IOBs it has only 500 not 900 as the part name would suggest.
 

If you check the FPGA ordering information section for the device mentioned above, you will find it has "900 pins". But all of them need not be "user IOs". My bad: I remembered from the time I was working on FPGAs around 5 years back that some info on IOs could be gleamed from the device name. So I thought of sharing it here. But basically using a bigger device is a solution to the problem here.
 

sharath666 said:
If you check the FPGA ordering information section for the device mentioned above, you will find it has "900 pins".
Click to expand...
Ha ha, funny you say that as if you think I don't know that the -FFG900 is the package information. FF is usually (but not always) a flip-chip package.

I remembered from the time I was working on FPGAs around 5 years back that some info on IOs could be gleamed from the device name.
Click to expand...
Wow, that's not a very long time...I don't think I've ever seen a part number that included the package type (basically the ordering code) that you could glean the actual number of user IO and I've been using and ordering FPGAs from nearly all the vendors since the Xilinx 2000 series days. The whole idea of the package code is so you can tell how many pins are on the device 900 v.s. 600 pins. How many IO is dependent on how many the vendor uses for power, ground, programming, reference voltages, and other non-user IO pins. This isn't like good ol 22V10 days... Oh look I have 22 pins I can use with up to 10 outputs. :)

Regards
 

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