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Empty flag generation issue in asynchronous fifo

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abhinavpr

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Hi,

I have designed an Async FIFO.

write clk = 50 Mhz

read clk = 10 Mhz

FULL flag is gnerated in wclk domain with synchronized read ptr.

FULL detection in immediate.

EMPTY flag is generated in rclk domain with synchronized write ptr.

here EMPTY condition is not immediate

as the write ptr is synchronized using 2FFs in read clk domain

and the value received is the value of write ptr 10wclk cycles earlier.

so while the FIFO is filled with 10 data EMPTY flag is raised.

I would like to know if there is any efficient way of generating EMPTY flag in async fifo.

-abhinavpr
 

It is not enough with a 2-stage synchronizer to transfer the pointers between the clock domains. You need Gray coding or a handshaking mechanism.

Otherwise, I think you have done it right.The empty flag can be set after new data has been written to the FIFO, but is it a problem? It will be cleared again 1-2 read clock cycles later.
 

Empty being high with data in FIFO is not a problem. It has to go low a few cycles later.The thing to take care while designing an ASYNC FIFO is that you should not lose any data. Delay in detecting a condition is never an issue.
 

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