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sine wave with difference amplitude in cadence

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matin-kh

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Hello,
I want to have such a sine wave like below to simulate my AGC, how can i have something like this in cadence?
sin.jpg

with warm regards
Matin
:)
 

I don't think that generating such file is easiest way :)

I usually write my own block in Verilog-A with my parameters.
But if you don't want do it, there is other way - in ahdlLib you can find "multiplier" block, connect to one from input pins Vsin, and source with modulating waveform to second, result - output sine with amplitude value sets by your modulating source.
 
With the Vsin source you can specify a time offset, an exponential damping factor (pos. or neg.), and/or a modulation frequency and -index, if this should be suitable for your application.
 
To generate sinusoid with linearly incresing amplitude You can used this simple python code:
Code: 
#!/usr/bin/env python

import math
from numpy import arange

def main():
	fileName=open("sinus.wfm","w")
	for i in arange(0,1800/math.pi,.1):
		fileName.write("%f %f\n"%(i,(1+1*i*math.sin(i))))
		
	fileName.close()
	
if __name__=="__main__":
	main()

The result of this code is file giving this waveform:
sinus.png
 
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