digital clock / data recovery for an ultra low power IC

Hi guys,

I'm going to design a clock/data recovery circuit for an ultra low power IC.
Data comes in a manchester coded packet with length of about 120 bits and data rate of 40 to 80 kbps. To reduce the power consumption, we have to turn off the digital section after processing the packet and turn it on again when a new packet arrives. Another module will take care of checking for new packet to turn on and off the clock/data recovery circuit.
We don't have an external clock source and just can have one RC oscillator with (+/-)25% of accuracy.
I think, the best solution is using a counter to extract the data rate from preamble
and then starts counting to that number to specify the right time for data sampling. Am I right? Is there any more efficient solution for this? Where can I find some document / book for digital clock data recovery?

I hope my question is clear enough, but if it is not, please ask to clarify it more.
Thanks in advance

You disappointed me guys !!
It seems that no one knowes how to deal with this problem, except myself

you could try and catch an edge on the data line using FF and xor...run a counter between to edges and check the count.

why low power
?
the lower the digital will quick
so except the pll
the cdr will more easy