Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Different timing constraints for timing paths in sequential circuits

Status
Not open for further replies.

Amir Yazdanbakhsh

Newbie level 5
Joined
Jun 18, 2013
Messages
9
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
66
Hi,

I am trying to synthesize a sequential circuit. Suppose the design has two outputs (out1, out2). I want to define different timing constraints for each of the outputs. By this, I mean for example to put timing constraint 0.5 for all the paths that lead to out1 and timing constraint 0.75 for all the paths that lead to out2. Following you can see my Verilog design:

Code:
module test(clk, a, b, c, out1, out2);

	input	clk;
	input 	a, b, c;
	output	out1, out2;


	reg a_reg, b_reg, c_reg;
	reg out1_reg, out2_reg;
	wire out1_w, out2_w;

	assign out1 = out1_reg;
	assign out2 = out2_reg;
	assign out1_w = ((a_reg & b_reg) | c_reg);
	assign out2_w = ((a_reg | b_reg) & c_reg);

	always @(posedge clk)
	begin
		a_reg <= a;
		b_reg <= b;
		c_reg <= c;
		out1_reg <= out1_w;
		out2_reg <= out2_w;
	end

endmodule
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top