Jester
Full Member level 6
Well known that CMOS gates should always be driven high or low and not allowed to have floating inputs causing excessive shoot-through current in the output stage.
What if the input is not a logic gate per se, but simply a digital input to a microcontroller, and the input signal (from the external world) has very slow transitions or sits at mid-scale?
Will this damage the device in the long term or is the current limited sufficiently in the FET immediately after the input stage?
Assume this is a regular digital input (no hysteresis) and the signal ends up being midscale regardless of pull-ups
What if the input is not a logic gate per se, but simply a digital input to a microcontroller, and the input signal (from the external world) has very slow transitions or sits at mid-scale?
Will this damage the device in the long term or is the current limited sufficiently in the FET immediately after the input stage?
Assume this is a regular digital input (no hysteresis) and the signal ends up being midscale regardless of pull-ups