Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

rising and falling time matching

Status
Not open for further replies.

william_luo

Junior Member level 2
Joined
Mar 25, 2013
Messages
23
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,283
Activity points
1,465
Hi, all

I have a question about transistors matching. For inverter, I know that the width ratio of pmos to nmos is nearly 2:1 (tsmc18) for getting equal rising and falling time. I just wonder, for other circuits, like NAND2 or XOR2, do I need to match transistors for worst case? (like NAND2 shown below, in this case, )

When I took this course in class, the lab tutorial just told me that for two input cases (NAND2 or XOR2), give one input VDD, change other input signal. But obviously, this is not the worst case. Can someone explain this for me? Thank you in advance.

Regards,
 

Attachments

  • nd2.jpg
    nd2.jpg
    5.9 KB · Views: 133
Last edited:

You attachment gives an "Invalid" message when I click on it. Go to the Go Advanced tab when posting and use the Attachments tab (paper clip) to reference an attachment.
 

Hi, all

I have a question about transistors matching. For inverter, I know that the width ratio of pmos to nmos is nearly 2:1 (tsmc18) for getting equal rising and falling time. I just wonder, for other circuits, like NAND2 or XOR2, do I need to match transistors for worst case? (like NAND2 shown below, in this case, )

Regards,

If it is really needed to match the rising and falling time of the nand2 gate (as an example) under all conditions , then we use symmetric gate type and then size the NMOS and PMOS properly.


nand_symmetric.png


Use this type of symmetric structure and then size the gates.
 

Thanks for your reply.
But I just wonder in which cases do I need to match the rising and falling time under worst case (or other conditions), or generally the matching work in the condition of giving one input VDD (NAND2) is enough?
 

The above mentioned type of symmetric nand gate will provide you equal rise and fall time in all the cases. The price you need to pay for this is higher no. of transistors.
Either this equal rise and fall time is required or not depends upon your requirement. Usually this is a rare requirement I believe.
 
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top