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Can i use VHDL code for describing a Device in OrCAD PSPICE A/D.

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root2hell

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i want to generate a high frequency say 30MHz RAMP.
 

What do you mean by: "RAMP"?
FPGA's can be used to model digital logic.
Analog circuits can't be modeled with the FPGA digital fabric.
 

I don't think Pspice supports simulation of VHDL code.
You can simulate circuits (Analog/Digital) having spice models.
 

veriloga is more likely to be supported. Still "code style"
but a lot of concept and syntax to digest in order to make
a realistic (in multiple analysis types) code-model. If you
are already good with VHDL it should not be hard to pick
up. Try searching for "veriloga ramp generator" and I'll bet
you can find plenty of examples out there (there is a
veriloga organization, forget the name, that had a decent
little repository of circuit function and analysis-support
code blocks. I'm sure you'll stumble across it in searching.
 

thanks for replies but actually i want to perform PWM for a class D amplifier. and i am having trouble in generating sawtooth.
 

If you insist to do it all in the digital domain, then a free running
counter and magnitude compare against some incoming data
word (representing the digitized audio) would do it.

Knowing only that you are "having trouble" doesn't help us.

Knowing your response to suggestions is only more complaints,
makes us disinclined to put more thought into it.
 

PWM is very possible and easy to do with FPGA/CPLD.
 

i want to do in OrCAD PSPICE and want to generate a 30 MHz sawtooth for that without use of VPULSE.
like integrating a square wave.
 

i want to do in OrCAD PSPICE and want to generate a 30 MHz sawtooth for that without use of VPULSE.
like integrating a square wave.
Why don't you do exactly this: integrating a square wave (using behavioral SPICE models). I don't see where VHDL comes into play.

You can model complete power electronic control circuits, e.g. PWM, feedback amplifiers etc.
 

it seems impossible for me to generate a 30MHz square wave in OrCAD.
 

I don't understand what's specifically impossible in this case. 30 MHz? Generating a square wave?

You'll need some kind of independent source in transient analysis, e.g. VPULSE. It's possible in principle to include some digital functions with PSPICE A/D, but I don't see an advantage in this case.
 

i can generate 2 MHz waveform using 555 timer but frequency will not go beyond 2 MHz.
ansd i dont want to use VPULSE coz its impractical.
 

i dont want to use VPULSE coz its impractical
Impractical in which sense?

Maybe the thread title is just misleading. If you want to design a hardware generator, it's essentially not a PSPICE problem. You can e.g. use a crystal oscillator with square wave output.
 

Seems like you want to defeat yourself very badly, if none
of these solutions appeal to you. The problem is simple and
there are many simple solutions but you don't like any of them.
So I think the problem is not with the circuit or the tools.
What is more important, getting the job done or humoring
your preconceptions of how it should? Because these latter
seem to be pretty vaporous.
 

i have tried this but failed... schematic.JPGschematic waveform.JPG
 

At first sight, I wasn't sure if you are using inverters with attached SPICE models, but the DC voltage level suggest you do.

It's apparenntly a trivial oscillator simulation problem. The initial transient solution puts the circuit in perfect equilibrium and it never starts to oscillate. Disabling the initial transisent solution (option UIC) is the most simple way to fix it, otherwise you need a "kickstart" pulse for the oscillator.
 

Review transient analysis options in your user guide. UIC is the name of the original Berkley SPICE option.

- - - Updated - - -

P.S.: The PSpice 7404 model doesn't seem to work for an oscillator.
 
i have used CD4049 CMOS logic and now it works but a maximum of 4.8MHz can be achieved coz of Large pd of CD4049.
even i cant get PSPICE model for a Fast CMOS Inverter.
where can i get a PSPICE Model for a fast say <10ns pd CMOS inverter
 

You must be using spice model for CD4049. May be you can try reducing W,L of nmos, pmos used in the model to reduce parasitics and so reduce overall delay.
 
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