Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

ic 2110 high side pwm delay

Status
Not open for further replies.

Rajnaveen

Member level 2
Joined
May 11, 2014
Messages
42
Helped
0
Reputation
0
Reaction score
0
Trophy points
6
Activity points
307
hi friends ,
I am using 2110 ic as a pwm for inverter mosfet , there is a problem that when initially input pwm is provided ic provide output after 150us what causes this problem and in this time i saw that bootstrap capacitor suddenly decrase the voltage level of dc supply for ic after few ms ic working is normal ..
what is solution...help ...me
 

Hi,

to charge the bootstrap capacitor you first need to activate the low side output for a short time. (read datasheet).

After that you can activate high side fet. Without delay.


------

if this is not the answer to your problem, then show us the schematic and some scope pictures and a more detailed description.


Klaus
 

hi friends ,
I am using 2110 ic as a pwm for inverter mosfet , there is a problem that when initially input pwm is provided ic provide output after 150us what causes this problem and in this time i saw that bootstrap capacitor suddenly decrase the voltage level of dc supply for ic after few ms ic working is normal ..
what is solution...help ...me
May i see your schematic ? how is your IR2110 configuration ? how much is value of your bootstrap capacitor ? how much is your PWm frequency how much is your modulation depth and what kind of mosfet you have used ?

Best Wishes
Goldsmith
 

Thanks for your reply .
Hi Goldsmith ;
I dont have the schematic right now but i can tell you detail ..Capacitor value is .1uf and 22uf in parallel .
Frequency of PWM is 20KHz . and Will you please explain me what is modulation depth ?
 

I dont have the schematic right now but i can tell you detail ..Capacitor value is .1uf and 22uf in parallel .
Use 100 uF instead of 22uF .
and Will you please explain me what is modulation depth ?
I mean your minimum and maximum value of duty cycle .
 

Hi,

goldsmith:
how much is value of your bootstrap capacitor ?

Rajnaveen:
Capacitor value is .1uf and 22uf in parallel .

goldsmith:
Use 100 uF instead of 22uF


are this the really values of bootstrap capacitor?

This is way too much. 0.1uF up to 1uF ceramics is good.

Klaus
 

are this the really values of bootstrap capacitor?

This is way too much. 0.1uF up to 1uF ceramics is good.

Klaus

Hi Klaus
I'm afraid but i disagree with you .
1uf or 0.1uf can't maintain charge for a long time so the bootstrap action won't be fulfilled as well so the circuit won't work as well if you use that cap as low as you mentioned furthermore , if use it with a low capacity then your H side will turn into linear region which is dissipative portion so the mosfet will deal with some hazards .
Best Wishes
Goldsmith
 

Hi

1uf or 0.1uf can't maintain charge for a long time
This is true, but how "long time" is it for a 20kHz PWM frequency?

It´s better to reccomend not to use 100% duty cycle.

if use it with a low capacity then your H side will turn into linear region
The IR2110 has undervoltage protection, so there is no danger to turn into linear region.


I also reccomend to keep on the manufacturers documents.

--> IR2110 datasheet
--> AN-978 HV Floating MOS-Gate Driver ICs
--> DT98- 2a Bootstrap Component Selection for Control IC’s.

Klaus
 

This is true, but how "long time" is it for a 20kHz PWM frequency?
Hi
You simply think that the issue is just about 20KHZ ?! what about leakage ? do a simple experiment . use 0.1u cap as you said and charge it and see the voltage across it using oscilloscope . what will happen ? frequency isn't the only important parameter the leakage must be calculated too .

It´s better to reccomend not to use 100% duty cycle.
Sorry but i think must learn about how a mosfet driver does work ! 100% D.C ?!! in that case how the bootstrap action would be fulfilled ? of course it won't do it's job ! furthermore the first post says it's for inverter okay ? in what kind of inverter you see the D.C about 100 percent ??!!
The IR2110 has undervoltage protection, so there is no danger to turn into linear region.
And in that case the circuit won't work as well as expected because it will stop switching isn't it ?

Best Luck
Goldsmith
 

Hi,

Well roared, lion.

All the information you are talking about can be found in the reccomended documents. ( even the calculations of the bootstrap Cs including leakage and frequency)
And i have the experience to say, that if one keeps on this information all will be good.

Let the people teach themselfes. With reliable informations from manufacturers with huge experience. From documents with detailed descriptions, all necessary formulas and a lot of background information. This wiil help them for years, and not only for one question.

So, don't be upset, this was not my intention.

Klaus
 

Hi

Well roared, lion.
Be careful of the phrases which you're using ! i suppose when you joined here you read the laws isn't it ? so watch your step .

All the information you are talking about can be found in the reccomended documents. ( even the calculations of the bootstrap Cs including leakage and frequency)
And i have the experience to say, that if one keeps on this information all will be good.
If you are familiar with bootstrap action why you talked about 100 percent D.C which is impossible for a bootstrap driver ?! indeed you need to learn !
Have a look into the other related threads of this forum you'll see a lot of similar things .

Let the people teach themselfes. With reliable informations from manufacturers with huge experience.
A simple thing : don't follow every thing blindly an example ? refer to the datasheet of UC3845 you'll see a diagram which presents how to use RTCT in order to make the frequency in your desired range . you know the result ? the result is that in datasheets which i've got those years which i guess they didn't improve it yet , that is all wrong ! if you go though it you'll see the frequency is two time less .

A question , have you ever found anybody which could do anything without any earned experience and just reading books and articles and datasheets ?!

So, don't be upset, this was not my intention.
And neither me
Good Luck
 

Hi,

..you read the laws isn't it ? so watch your step .
i´m sorry. i didn´t know that it´s not allowed to quote Shakespeare.

indeed you need to learn !
As i recommended not to use 100% duty cycle...
1) i knew it is an often made mistake with bootstrapping, (often occasionally, when one builds a regulation loop and it´s (clipped/saturated) output leads to 100% duty cycle)
2) it shows that i´ve already learned this...

Would you also complain if i recommend not to touch a 10kV wire?

The 100% duty cycle came into my mind, because with 20kHz the bootstrap gets charged every 50us.
For me this is not a long time. Now you speak of "long time". So i looked for a case where with a 20 kHz PWM the time between two charge cycles is more than 50us.
My conclusion was that only 100% duty cycle can generate this situation. (i know 100% duty cycle isn´t truely a PWM).

An objective way for informations are calculations:
I estimate time to it´s worst case with 20kHz: 50us
I use a 1uF capacitor
And i estimate the leakage current to be 100uA. (also about worst case)
C = I * t / dU ==> dU = I * t / C = 100uA * 50us / 1uF = 5mV.
Maybe i´m wrong, but 5mV of voltage drop caused by leakage current under worst case conditions isn´t much.

refer to the datasheet of UC3845
I make mistakes, you make mistakes, everyone makes mistakes. And therefore it is not unusual that there are mistakes in datasheets.

In my eyes the datasheets of the manufacturers are the best source of information (although there may be some mistakes).
Do you know more reliable sources of information?


**
to end our personal "bootstrap story":
is why humans should fight..
I never intended to fight against you, but to give the OP helpful assistance.
So let´s shake hands.
With honest regards

Klaus
 

I agree that there's no reason to argue.

Technically the contradicting posts are possibly assuming different operating conditions, I think.

case 1: You have 20 kHz PWM without gaps, in other words the PWM duty cycle ("modulation") is staying below an upper limit of e.g. 95 or 98 % kept by the controller . The bootstrap capacitor will be recharged pulse-by-pulse. The size of the bootstrap capacitors is commanded by the total gate charge, driver DC-current*pulse period and acceptable voltage drop. 1 µF is sufficient in usual cases.

case 2: You have 20 kHz PWM with periodical gaps caused by overmodulation or dedicated modulation methods like "flat top". The bootstrap capacitor must additionally store the charge for DC-current*gap length. A high µF value may be required.

For lack of detailed results (e.g. oscilloscope waveforms), it hasn't been clarified that the original "150 µs delay" problem is related to bootstrap capacitor size at all.
 
Hi again
Sorry that i was absent for a long time . i know this issue is somehow solved in this topic but i should say something :
i´m sorry. i didn´t know that it´s not allowed to quote Shakespeare.
I really didn't know that , that sentence is for Shakespeare so no problem with that ;-)
As i recommended not to use 100% duty cycle...
1) i knew it is an often made mistake with bootstrapping, (often occasionally, when one builds a regulation loop and it´s (clipped/saturated) output leads to 100% duty cycle)
2) it shows that i´ve already learned this...

Would you also complain if i recommend not to touch a 10kV wire?

The 100% duty cycle came into my mind, because with 20kHz the bootstrap gets charged every 50us.
For me this is not a long time. Now you speak of "long time". So i looked for a case where with a 20 kHz PWM the time between two charge cycles is more than 50us.
My conclusion was that only 100% duty cycle can generate this situation. (i know 100% duty cycle isn´t truely a PWM).

An objective way for informations are calculations:
I estimate time to it´s worst case with 20kHz: 50us
I use a 1uF capacitor
And i estimate the leakage current to be 100uA. (also about worst case)
C = I * t / dU ==> dU = I * t / C = 100uA * 50us / 1uF = 5mV.
Maybe i´m wrong, but 5mV of voltage drop caused by leakage current under worst case conditions isn´t much.
I know about these calculations but my meaning was not just leakage . gate current is important too . and a lot of parameters . i agree the calculated cap may be low but as FvM said (case2) i was referring to such a issue but i couldn't transfer my meaning as well .

make mistakes, you make mistakes, everyone makes mistakes. And therefore it is not unusual that there are mistakes in datasheets.
Certainly ! nobody is complete human means a lot of mistakes while growing process .

So let´s shake hands.
With honest regards
I agree that we must shake hands and be friendly . sorry if my words were not good . :-D

With a lot of regards
Goldsmith



case 2: You have 20 kHz PWM with periodical gaps caused by overmodulation or dedicated modulation methods like "flat top". The bootstrap capacitor must additionally store the charge for DC-current*gap length. A high µF value may be required.

For lack of detailed results (e.g. oscilloscope waveforms), it hasn't been clarified that the original "150 µs delay" problem is related to bootstrap capacitor size at all.
I highly believe in this issue ! almost all of my similar problems with bootstrap drivers were related to the bootstrap capacitor too .


Best Wishes to all
Goldsmith
 

Hi,

Shaking hands arrived. :smile:

With regards.

Klaus
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top