sajjaudaykumar
Junior Member level 1
Hi,
I heard that LOS causes fake failures on tester due to the fact that it tends to test fake transition(I heard of it somewhere). The reason being it sets up value easily because it is done during shift and ATPG tool has full control. Were as in LOC the vector V2 sets it up in functional mode.
I am not sure how this can be when we are using SDC for ATPG? After all we are setting up the value on Q pin? Is it true.
I heard that LOS causes fake failures on tester due to the fact that it tends to test fake transition(I heard of it somewhere). The reason being it sets up value easily because it is done during shift and ATPG tool has full control. Were as in LOC the vector V2 sets it up in functional mode.
I am not sure how this can be when we are using SDC for ATPG? After all we are setting up the value on Q pin? Is it true.