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Assura LVS issue with IBM cmrf7sf

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oucd

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I used netSet to pass the global power (VDD!) and ground (GND!) of a top cell (called inherit) to a lower level cell (called INVERT_A) . VDD! and GND! were passed correctly in the schematic. When I proceeded to LVS and looked at the LVS schematic netlist and layout netlist, I realized that the global power (VDD!) and ground (GND!) were not being passed on. Even though looking at the layout that VDD! is tied to the NWELL and GND! is tied to the substrate, the LVS still complains of open connections.

Would someone be able to help me with this LVS issue? Please see the attached files.
Thank you.
 

Attachments

  • LVS issue netSet.pdf
    526.3 KB · Views: 154
  • inherit_cls.pdf
    9.4 KB · Views: 104

Have You correct pins/labels (gnd, vdd) placed on the lowest level cell INVERT_A? It would be better if You will post your layout screenshot.
 

VDD! and GND! are the power and ground pins. A and Z are input and output pins.
The VDD! is tied to the NWELL and GND! is tied to the substrate.
 

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  • Layout.png
    Layout.png
    24.5 KB · Views: 114

erikl said:
Seems UPPER and lower case letters will be distinguished: View attachment 107783
Click to expand...

Possible solutions:

1. Make sure pin name in Schematic and layout are same...if u r using capital letters in schematic then layout pin also same as schematic.
2. Make sure pin connection in layout should be at the top most level. If the pins are in bottom level it will not work at top level.
3. Pin name in layout should be metal pin ...make sure if u r placing the pin on metal1 then pin should be metal1 pin if u r placing pins on metal 2 then pin name should be metal2 pin.


by seeing attachment what i understood is ur pins in schematic is in small letter and in layout it is in capital letter
 

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