Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Query on Latch/ICG timing

Status
Not open for further replies.

mvasanth

Newbie level 3
Joined
Feb 19, 2014
Messages
4
Helped
4
Reputation
8
Reaction score
4
Trophy points
3
Activity points
34
Hi all,

I have two questions :

1). We know about the time borrowing from a latch, so is the borrowing inferred during timing analysis by the tool or inference comes from a lib?

2). Similarly we know that a clock gating cell is made up of a latch and an combo gate, so can time be borrowed from the ICG as well?


Thanks in advance for your responses.
mvasanth
 

HI,

1. Time borrowing needs to be enabled by the user .libs have no information about time borrowing. The tool understands the a latch based design and if time borrowing is enabled then it will optimize the design accordingly depending on the combo logic between the two latches
2. Yes time borrowing can be implemented for ICGs as well.

srp8514
 
Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top