Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Help me with delaying a clock in simple SPI interface

Status
Not open for further replies.
M

Mercury

Member level 3
Joined
Oct 7, 2003
Messages
67
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
612
simple spi

Hi!
I'm writing a simple SPI master interface in VHDL for a Coolrunner II CPLD. The clock rate is no higher than 20MHz. The data on MOSI line needs to appear a few ns before the rising edge of the clock, in order for the slave to catch the data.. But since the SCK line and the clock feeding the shift register are the same, the data will appear simultaniously with the clock (or even worse, the data will be delayed ). So the clock needs to be delayed with regard to data, but how is this achieved?

Best regards
George
 

Re: Simple SPI Interface

Why not just output the data on the falling edge?
 

Re: Simple SPI Interface

That would work, but when starting a transmition, how would know that the rising edge of clk will come before the falling edge? If the falling edge arrives sooner, that the first bit won't be shifted out.
 

Re: Simple SPI Interface

You said master, so that means you provide the clock doesn't it?

But if you only have a 20MHz master clock, and you want to provide a 20MHz SPI clock I think that's pretty hard to do well. You should have a 40MHz master clock input to the CPLD and generate the 20MHz SPI clock from that.

Then, generate your SPI clock, data and chip-selects using a small state machine.

Output new data and lower clock on one cycle, raise clock on the next, repeat.
 

Simple SPI Interface

Do you have finished your work yet ? could you upload the sources ? THX
 

Re: Simple SPI Interface

u can check xilinx website.
there is an appnote on spi master implementation in coolrunner-II
also source code can be downloaded for free
 

Simple SPI Interface

That is what I've... uuhhh....

I redone It myself.... I will put my works here as soon as possible
 

Simple SPI Interface

Why dont use 100MHZ general clock and scale down 20MHZ to SPI clock?
 

Re: Simple SPI Interface

There is a free SPI design at opencores.org.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top