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Which type of ADC consumes least power?

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Debdut

Debdut

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I'm trying to design an ADC in subthreshold region of operation of the MOSFET. It should consume least amount of power.

I searched the web and found ADC types - SAR, Wilkinson, Dual-slope, ∑-Δ, Flash, etc. I also found a paper entitled "An 8-Bit Single-Ended Ultra-Low-Power SAR ADC With a Novel DAC Switching Method and a Counter-Based Digital Control Circuitry" from IEEE. The ADC they designed consumes 101 nW power. I haven't fully read the paper but I understand SAR ADC requires extra hardware like an additional controller etc.

So my question is - which type of ADC I should design? :-?
 

Hi,

There are many parameters to consider to find the "ADC with the lowest power".

Some are:
* resolution
* precision
* sampling frequency
* supply voltage
* signal voltage
...

And additionally:
* active analog signal filters
* preamplifiers
* sample and hold circuit
* multiplexers
...

But the next to consider is:
You design a super low power ADC. The data are fed to a microcontroller or something else to transmit or data processing.
Then this device must also designed to consume only the same ammount of power, otherwise it is not worth the effort of designing that ADC.

So, please give us more information about your project. (technical data and ideas)

Klaus
 

OK

VDD = 0.5 V
Power = Maximum of 1 µW
Resolution = 8 bits
Input Analog signal from a Variable Gain Amplifier with signal range from 0 to 100 mV. VGA power dissipation is usually large when designed in Saturation region, usually in milliWatts. Don't know what the power dissipation will be in Subthreshold region. :!:
Output digital signal to a FSK modulator whose specifications are still to be decided.

This much I can tell.
 

Hi,

VDD: 0.5V...

ADC power: max 1uW
compared to
VGA power: 1000 uW

does all this make sense?

----------------------

In my eyes the sampling frequency is still important:
If you need 1MS/s then i think it is not possible with 1 uW

If you need 1 conversion every minute (for room temperature regulation for example) you can power down most of the ADC for most of the time.
The power consumption then is dominated by the idle current.

Klaus
 

Each gate has a charge and resistance and voltage or pJ of energy required to toggle.

So without the resolution and frequency requirements, nothing can be designed.
 

Klaus,
The VGA power will decrease when designed in Subthreshold region. I wrote that the power dissipation is in milliWatts when designed in Saturation region. The power for all designs is in the order of microWatt in Subthreshold region.

And I'm thinking of designing the ADC for 50 kS/s. Today I found a paper where they designed a SAR ADC dissipating 78 nW power giving 17kS/s.
 

Hi,

i´m not experienced in ASIC design.

for 50kS/s i dont think dual slope is suitable, because it is too slow.
also flash is not suitable because of power consumption.

SAR seems possible, especially when i read 78nW in your post ...

Good luck

Klaus
 

Thanks for your comments...
 

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