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Using multiplexers as latches

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George_P

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Hi,

I am trying to figure out what are the possible problems you could get if you connected a mux output to one of its inputs.

So that when "select" is '0' it passes input1, otherwise it keeps the output value.

I know that it's a combinatorial loop and EDA tools might complain, but how on earth could you get an unstable/oscillating situation with such a configuration on silicon?

Any ideas?
/George
 

The only way I can see a problem occurring is if the routing delay from the output back to the input is longer than the high-low + low-high propagation delay through the multiplexer (plus any required high/low pulse width requirements). That would allow both a high-low and a low high transition to propagate around the feedback loop.
 
"Such a configuration on silicon" is known as a latch. If you use a latch then Static Timing Analysis will replace it with the timing model that was extracted from the layout of the latch cell and everything will work fine. The ATPG test tools will understand its function and create automatic tests. The tools will not only complain, they will not work.

How would perform STA and Test on a mux?
 

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