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How to reduce offset in a folded cascode opamp?

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lunarsurfer90

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I am designing a standard band-gap reference. A very crucial part of the design is obviously the opamp which would need to have very low offset. I have created a folded cascade opamp with pmos diff input. I have achieved about 1mV offset error with large input pmos diff pairs. Can I reduce the input diff pair size and increase the current source transistor sizes to achieve the same performance? If you can provide a link to some text or refer me to some book that would be great. I have looked at Razavi, etc. but couldn't find a discussion.
 

lunarsurfer90 said:
Can I reduce the input diff pair size and increase the current source transistor sizes to achieve the same performance? If you can provide a link to some text or refer me to some book that would be great.
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Reducing the input diff pair size is counter-productive to offset voltage, increasing the current source transistor size doesn't help against.

David M. Binkley "Tradeoffs and Optimization in Analog CMOS Design" (among many other features) extensively examines (offset) mismatch. Here's a tiny snippet from this book: offset-error_vs_drain-current.png .
 

Reducing input pair transistor size is not a good solution. Ideally this will make your offset to further increase in the silicon. Thus it is recommended to keep the device size big ..finish the layout with common centroid technique for offset reduction.
 

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