ERROR while BUILD using TetraMAX

Hi ,

this is my program

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;


entity full_adder_4bit_2 is
port (a,b : in std_logic_vector(3 downto 0);
Cin : in std_logic;
S : out std_logic_vector(3 downto 0);
Cout: out std_logic);
end full_adder_4bit_2;

Architecture df of full_adder_4bit_2 is

component full_adder
port (a,b,Cin : in std_logic;
S,Cout: out std_logic);
end component;

signal n1: std_logic_vector(4 downto 0);

begin

n1(0) <= Cin;
Cout <= n1(4) ;

ssa: for I in 0 to 3 generate

sa: full_adder port map(a(I),b(I),n1(I),S(I),n1(I+1));
end generate ssa;

end df;



I am getting the following error

What I thought the tool is not recognizing for generate statement



BUILD-T> read_netlist /home/ee75400z/Lab1/VHDL/full_adder_4bit_2.vhd
Begin reading netlist ( /home/ee75400z/Lab1/VHDL/full_adder_4bit_2.vhd )...
Error: Line 27 (/home/ee75400z/Lab1/VHDL/full_adder_4bit_2.vhd), missing definition (Component "ssa" is of undefined entity "for"). (N7-7)

Error: Line 32 (/home/ee75400z/Lab1/VHDL/full_adder_4bit_2.vhd), parsing error (expected "library_unit" got "end"). (N1-56)

Error: Line 32 (/home/ee75400z/Lab1/VHDL/full_adder_4bit_2.vhd), parsing error (expected "block end_of_file" got "df"). (N1-57)

Error: Line 32 (/home/ee75400z/Lab1/VHDL/full_adder_4bit_2.vhd), parsing error (expected "block end_of_file" got ";"). (N1-58)

I checked and it works fine in Xilinx ISE but no idea about why it's happening in TetraMAX.

kaiserschmarren87 said:

I checked and it works fine in Xilinx ISE but no idea about why it's happening in TetraMAX.

Click to expand...

that's what made me wonder :shock:

I guess Tetramax has a poor VHDL parser

what if figured out is in the synthesized netlist we dont have loops so that's why its not recognizing for generate loop

yes, but that has nothing to do with the problem here. Generate loops are unrolled in the elaboration and synthesis phase, and have nothing to do with the netlist.

Hence this tetramax synthesisor is really bad.

Xilinx, Altera, Synplify have not problems with generate loops, and havent done since Ive been writing VHDL.