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Max Transition Violation Fix

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VLSI_Designer

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max transition violation

Hi ,

I would like to know the causes for the Max transition time violation ???

I heard that two reasons may lead to this violation
1) input delay of the pin is very high ( more than ) the set value in libary
2) do the wire length that leads to the delay.

I would like to know in each case how design compiler would try to fix the violation ! Especially Max Transition Violation.

When to use Gate Sizing and buffering ???
## got confused with these doubts.. and related material is highly appreciated. ###

Thanks
Vlsi_Designer
 

transition violation

for input, because you have set _dont_touch for the IO cells, so you should not care about them.

for inner violation, you should anlysis them according to the clock frequency. For better waveform, transition should not be more than 20% of the period.
 
max transition

I also think the max transition is not related with the
input delay...

The max transition is decided by:
(1) input port transition;
(2) input clock transition; (important)
(3) wire length...
(4) Fanout...
(5) Gate drive strength...

wish help you...
To fix max trans vio,
just increase the output driver strength...
but size will increase...

So it is better to consider the function when fix the
max tran vio,....
 
max transition time violation

the transition is decided by two factors: one is the input slew (transition), one is output load(including wire cap and fanout).
If anyone of them is over the limit of Lookup Table in std cell library, inaccuracy is produced. So, fixing max_transition violation is inevitable.
If input slew is too slow, increment the driver strength.
If output load is too high, add some buffer.
Now, you need look into these two factors.
 
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