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How to define input slew rate range when doing standard cell characterization?

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Brucecwang

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Hi,

When using Siliconsmart or ELC to characterize standard cells to generate .lib, how to define the realistic input slew rate range for the delay/power lookup tables?

In practice, is it to use spice simulation to measure the slew rates of standard X4 invertor/buffer from FO1 to FO10? Or any other standard way adopted and used by standard cell vendors?

Thanks.
Bruce
 

For a 0.18um commercial standard cell library, from spice simulation of a minimized buffer driving 10 X4 buffers (in the .lib, the max fanout is defined as 10)，the slew rate is less than 1ns. But in the .lib, the input slew range of the timing & power table for all cells is from 0.05ns up to 4.5ns.

Anybody have any idea for this? Thanks in advance.
 

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