kurtulmehtap
Member level 3
Hi All,
We have a QPSK modulated signal 700 Mhz IF, 80Mhz BW to demodulate.The bit rate is 100 Mbit, roll-off is 0.65.
Now we have to select an RF-ADC,FPGA board to demodulate it.
The RF part can be handled by an I&Q demodulator circuit.
Our question is; what should be the minimum sampling rate of the ADC's?
What should be their minimum clock frequency?
Thank you.
We have a QPSK modulated signal 700 Mhz IF, 80Mhz BW to demodulate.The bit rate is 100 Mbit, roll-off is 0.65.
Now we have to select an RF-ADC,FPGA board to demodulate it.
The RF part can be handled by an I&Q demodulator circuit.
Our question is; what should be the minimum sampling rate of the ADC's?
What should be their minimum clock frequency?
Thank you.