Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
You need to analyze why this slew violation appears.
is it on a macro pins? std-cell, same types, long routing?...
You will understand why the tool behave like this.
Do you create the clock tree in MMMC mode?
And how much the violation is ? (%)
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.