Issue with half-bridge gate drive

Hi, looking for help on my gate driver + FET circuit.

The issue is that the node between the FETs of the half-bridge drops to about -8V relative to the GND of my gate driver when the top FET turns off. I believe that this is largely due to the parasitic inductance of the circuit in combination with the very high current I am driving (~500A), aswell as the effect of the low-FET body diode beginning conduction. Now, this -8V relative to gate driver ground is bad for the SH_x pin of my gate driver and may be the reason I keep frying it. So, to solve this, I have installed a diode between the SH_x pin and gate driver ground, which keeps the SH_x pin from dropping below -0.7V. I also have a small 1Ohm resistor between the SH_x pin and the 'node' point between the two FETs to limit current through the diode when it is conducting.

The problem and this solution are summarized on page 12 of this document:
https://www.fairchildsemi.com/an/AN/AN-6076.pdf

So, the diode+resistor solved the negative transient on SH_x problem but has introduced another. Now, the high FET is slow to turn off resulting in large switching loss (heat). I believe this has occurred because if the high FET tries to turn off quickly (high di/dt), it's source voltage drops negative, increasing Vgs and slowing the turn-off. Since the gate driver cannot provide anything to the high FET gate below -0.7V, it is now limited in its ability to turn it off. This is my theory.

To alleviate this, I have put a 1ohm in series with the diode, which now allows a minimum of -3V on the SH_x pin. This has improved the situation a bit, acting as a compromise but it's not ideal.

I am looking for any comments or suggestions on how else I might go about fixing my problem.

Thanks.

Hi,

-8V ... either this is only in a very short time caused by induction, or it is a general layout problem.

So a screenshot of your oscilloscope can give more information to us.
Also helpful is a picture of your whole circuit including scope connections and your schematic.

With the layout you must use signal planes for the high power load, and in addition you need extra wiring for the driver signals. Usually the drivers GND has a low impedance connection directely to the source pin of the low side FET. This line must not see any of your load current and the reverse current caused by a conductive body diode.
In the same way this is true for the driver to source connection of the high side FET.

Short wiring maybe 10mm, and wide traces.

The internal body diode usuallly is slow with reverse recovery, therefore it could be necessary to externally connect a fast schottky diode in parallel. This depends on switching times and fet data ... and reduces EMI and heating.

Hope this helps
Klaus

Edit1: spelling

Hi, thanks for your reply.

Yes, the negative transients only last for about 300-500ns. A negative transient is also present on the SL_x pin (at low FET source), though to a lesser degree (-3.5V instead of -8V relative to gate driver GND). I have attached a scope shot of the transients, which occur just after the high FET turns off.

Since I am driving a three-phase load, there are actually three half H-bridges, with a single gate driver IC for all phases. So, I cannot connect the gate driver GND to the source pins of all phases directly. Instead, it is connected as close as I can to a common point between the low-FET sources of each phase. Since the negative transients are present at the actual FETs themselves (seen by measuring Vds), I don't think they have to do with the wiring from the gate driver to the FETs. Since each phase has a low-side current sense resistor, I believe the inductance of these are contributing to the negative transients.

I looked into schottky diodes in parallel with the FETs, but in order to handle the huge currents, they would have to be physically huge (the same size as my FETs - TO263) and there is no room in my layout for these. Each inverter leg has five parallel FETs to handle the 500A peak phase current.

Thanks!

Centmo said:

Since each phase has a low-side current sense resistor, I believe the inductance of these are contributing to the negative transients.

Click to expand...

Definitely YES. Some years ago metal strip shunts had the least inductance... but also the connection to the power plane is critical. If you can handle the soldering, then i recomend to avoid thermal pads.

Schottky diodes: usually the are conductive only a short time, therefore you have to look for "peak currents" in their datasheets and not continous current. Heatsink may be required.

Five FETs in parallel: Every FET with its own driver?

Hint: just to test if the scopes probe and the GND connection works good and additionallly the inductive influence to the probe is low id try to connect the Probe´s tip to a GND pin near your desired signal pin. Ideally you will see a flat line at zero. What you really see gives you a sense on how to interprete the signals on the scope.

Hope this helps

Klaus

You should show a schematic that clarifies the node names in the description and oscilloscope waveforms.