Need Verilog/Code for Router

Similar threads

• K

  explanation of how to translate C code into verilog

  • Started by keikaku
  • Mar 5, 2024
  • Replies: 10

  PLD, SPLD, GAL, CPLD, FPGA Design
• A

  How can I run verilog code with data at a specific time in the past?

  • Started by alexis57
  • Jan 28, 2024
  • Replies: 2

  PLD, SPLD, GAL, CPLD, FPGA Design
• E

  The question for Verilog math question

  • Started by EDA_hg81
  • Sep 8, 2023
  • Replies: 0

  PLD, SPLD, GAL, CPLD, FPGA Design
• S

  Cannot identify inferring latches in code

  • Started by sims0702
  • Apr 12, 2024
  • Replies: 10

  PLD, SPLD, GAL, CPLD, FPGA Design
• M

  How do I assign decimal values in verilog?

  • Started by mahesh_namboodiri
  • Jan 31, 2024
  • Replies: 2

  PLD, SPLD, GAL, CPLD, FPGA Design